Abstract:
A method of measuring changes in signal level output of an integrated circuit sensor by providing a direct current (DC) or low frequency (AC) bias to the sensor and placing a floating gate semiconductor device on-chip and coupling the floating gate of the semiconductor device with the sensor. As a result, changes in signal level output of the sensor modulate charge at the gate. The semiconductor device in turn converts the modulated charge at the gate into output signals proportional to the changes in the signal level output. The measurement method provides a resolution in the sub-atto range.
Abstract:
Disclosed are apparatus and methods for efficiently writing states to one or more magneto-resistive elements. In one embodiment, current switches are provided for directing a write current through a number of write lines to control the write state of the magneto-resistive elements. In another embodiment, a sense current is selectively controlled to control which magneto-resistive elements are written to a particular state. In both embodiments, a latching element may be used to sense the state of the magneto-resistive elements, and may assume a corresponding logic state.
Abstract:
Embodiments of present invention provide a method and system for collecting, transmitting, editing and integrating, broadcasting, and receiving signals. The method comprises acquiring one and/or more audio signals and one and/or more video signals or the one program collected by one and/or more audio and video collection terminals; editing and integrating the one and/or more audio signals and the one and/or more video signals or the one program on a network platform, and then broadcasting; selecting among the one and/or more audio signals and the one and/or more video signals for the one program at a receiving terminal, and receiving the selected audio signal and video signal.
Abstract:
The present invention relates to a water-based pore sealing agent enhancing PCB coating anti-oxidation and anti-corrosion properties, consisting of, by weight, 4-12 parts of a corrosion inhibitor, 15-25 parts of a mixed surfactants system, 10-20 parts of an ion chelating agent, 6-15 parts of a pH regulator, 20-40 parts of a builder, and the rest being purified water. When used to perform pore sealing on a PCB, the water-based pore sealing agent is diluted with purified water first to be diluted 10-100 times, preferably, 100/8-100/3 times. The pH value is 7-11, and is preferably 7.5-9.5. The surface tension is 18-28 dyn/cm. The pore sealing treatment uses a immersion process, and preferably ultrasonic waves are added at the same time to assist in cleaning the pores. For the pore sealing treatment, the temperature is 20-60° C., and the time is 60-150 seconds. After pore sealing, the temperature for drying the coated piece is 80-150° C., and the time is 60-120 seconds. The PCB treated with the water-based pore sealing agent of the present invention undergoes the neutral salt spray test, the nitric acid vapor test, the mixed gas test, and the sulfur dioxide and bonding tensile strength test, and the results have indicated that the anti-oxidation and anti-corrosion properties of the coating thereof are significantly enhanced.
Abstract:
Exemplary embodiments for providing multi-bit error correction based on a BCH code are provided. In one such embodiment, the following operations are repeatedly performed, including shifting each bit of the BCH code rightward by 1 bit while filling the bit vacated due to the rightward shifting in the BCH code with 0, calculating syndrome values corresponding to the shifting of the BCH code, and determining a first error number in the BCH code under the shifting based on the syndrome values corresponding to the shifting of the BCH code. In the case where the first error number is not equal to 0, modified syndrome values are calculated corresponding to the shifting of the BCH code. The modified syndrome values are those corresponding to the case that the current rightmost bit of the BCH code under the shifting is changed to the inverse value. Additional operations are performed as described herein.
Abstract:
An improved grid for a nuclear reactor fuel assembly that has an egg-crate base grid as the primary support structure with each support cell of the base grid that supports a fuel rod having a lock-support sleeve that is rotatable within the support cell between a first and second orientation. In the first orientation the lock-support sleeve fits loosely within the support cell of the base grid and respectively, loosely receives the fuel rods that are loaded therein. The lock-support sleeves are then rotated to a second orientation that locks the fuel rods axially within the support cells.
Abstract:
The present invention relates to a water-based pore sealing agent enhancing PCB coating anti-oxidation and anti-corrosion properties, consisting of, by weight, 4-12 parts of a corrosion inhibitor, 15-25 parts of a mixed surfactants system, 10-20 parts of an ion chelating agent, 6-15 parts of a pH regulator, 20-40 parts of a builder, and the rest being purified water. When used to perform pore sealing on a PCB, the water-based pore sealing agent is diluted with purified water first to be diluted 10-100 times, preferably, 100/8-100/3 times. The pH value is 7-11, and is preferably 7.5-9.5. The surface tension is 18-28 dyn/cm. The pore sealing treatment uses a immersion process, and preferably ultrasonic waves are added at the same time to assist in cleaning the pores. For the pore sealing treatment, the temperature is 20-60° C., and the time is 60-150 seconds. After pore sealing, the temperature for drying the coated piece is 80-150° C., and the time is 60-120 seconds. The PCB treated with the water-based pore sealing agent of the present invention undergoes the neutral salt spray test, the nitric acid vapor test, the mixed gas test, and the sulfur dioxide and bonding tensile strength test, and the results have indicated that the anti-oxidation and anti-corrosion properties of the coating thereof are significantly enhanced.
Abstract:
The embodiments of the present invention provide a cellular power supply network, an intelligent gateway and a power supply control method thereof. The cellular power supply network further comprises: at least one cellular power supply layer formed by a plurality of transformers connected as a cellular structure. In the embodiments of the present invention, the electricity energy can be transferred from one transformer to another transformer demanding power as needed, so that the power is more reasonably distributed and the energy utilization rate is improved. In the technical solutions of the present invention, when a certain transformer cannot work normally due to a fault, the electricity energy outside the transformer can be introduced into the user of the transformer using the cellular power supply network, so as to keep continuous power usage. Meanwhile, the transformer can be separated from the power supply network for repairing and maintenance.
Abstract:
A magnetic memory device includes a first electrode separated from a second electrode by a magnetic tunnel junction. The first electrode provides a write current path along a length of the first electrode. The magnetic tunnel junction includes a free magnetic layer having a magnetization orientation that is switchable between a high resistance state magnetization orientation and a low resistance state magnetization orientation. The free magnetic layer is spaced from the first electrode a distance of less than 10 nanometers. A current passing along the write current path generates a magnetic field. The magnetic field switches the free magnetic layer magnetization orientation between a high resistance state magnetization orientation and a low resistance state magnetization orientation.
Abstract:
Method and apparatus for writing data to a storage array, such as but not limited to an STRAM or RRAM memory array, using a read-mask-write operation. In accordance with various embodiments, a first bit pattern stored in a plurality of memory cells is read. A second bit pattern is stored to the plurality of memory cells by applying a mask to selectively write only those cells of said plurality corresponding to different bit values between the first and second bit patterns.