公开(公告)号：US20200310754A1

公开(公告)日：2020-10-01

申请号：US16367672

申请日：2019-03-28

申请人： Arm Limited

发明人： David Raymond LUTZ

IPC分类号： G06F7/485 ,  G06F7/499

摘要： A floating-point adding circuitry is provided to add first and second floating-point operands each comprising a significand and an exponent. Alignment shift circuitry shifts a smaller-operand significand to align with a larger-operand significand, based on an exponent difference. Incrementing circuitry generates alternative versions of the larger-operand significand, each version based on a different rounding increment applied to the larger-operand significand. A number of candidate sum values are generated by adding circuits, each candidate sum value representing a sum of the shifted smaller-operand significand and a respective one of the alternative versions of the larger-operand significand. One of the candidate sum values is selected as a rounded result of adding the first and second floating-point operands. This allows floating-point addition to be performed faster as the latency of the rounding increment can be hidden in the shadow of the latency of the alignment shift.

公开(公告)号：US20190121615A1

公开(公告)日：2019-04-25

申请号：US15793063

申请日：2017-10-25

申请人： ARM LIMITED

发明人： David Raymond LUTZ

IPC分类号： G06F7/485 ,  G06F7/499

摘要： An apparatus and method are provided for subtracting a first significand value of a first floating-point operand and a second significand value of a second floating-point operand. Significand shift control circuitry asserts a shift signal when a difference is detected between at least one corresponding low order bit in the exponent values of the two floating-point operands. First processing circuitry is arranged to produce a first difference value by performing a first subtraction operation to subtract the second significand value from the first significand value when the shift signal is unasserted, and to subtract a right-shifted version of the second significand value from the first significand value when the shift signal is asserted. Second processing circuitry is arranged to produce a second difference value by performing a second subtraction operation to subtract the first significand value from the second significand value when the shift signal is unasserted, and to subtract a right-shifted version of the first significand value from the second significand value when the shift signal is asserted. First shift estimation circuitry is arranged to determine, from the significand values subjected to the first subtraction operation, a first estimated left shift amount, and similarly second shift estimation circuitry is arranged to determine, from the significand values subjected to the second subtraction operation, a second estimated left shift amount. Shifted difference value generation circuitry then produces, as a shifted difference value, the first difference value left shifted by the first estimated left shift amount when the first difference value is non-negative, and the second difference value left shifted by the second estimated left shift amount when the second difference value is non-negative. Such an approach can significantly reduce the time taken to generate a normalised difference value.

公开(公告)号：US20180307488A1

公开(公告)日：2018-10-25

申请号：US15494946

申请日：2017-04-24

申请人： ARM LIMITED

发明人： Neil BURGESS ,  David Raymond LUTZ ,  Javier Diaz BRUGUERA

IPC分类号： G06F9/30

CPC分类号： G06F9/3001 ,  G06F7/00 ,  G06F9/30032 ,  G06F9/30036

摘要： An apparatus has processing circuitry comprising an L×M multiplier array. An instruction decoder associated with the processing circuitry supports a multiply-and-accumulate-product (MAP) instruction for generating at least one result element corresponding to a sum of respective E×F products of E-bit and F-bit portions of J-bit and K-bit operands respectively, where 1

公开(公告)号：US20180217815A1

公开(公告)日：2018-08-02

申请号：US15833372

申请日：2017-12-06

申请人： ARM Limited

发明人： Christopher Neal HINDS ,  Neil BURGESS ,  David Raymond LUTZ

IPC分类号： G06F7/57 ,  G06F17/16

摘要： An apparatus and method are provided for processing input operand values. The apparatus has a set of vector data storage elements, each vector data storage element providing a plurality of sections for storing data values. A plurality of lanes are considered to be provided within the set of storage elements, where each lane comprises a corresponding section from each vector data storage element. Processing circuitry is arranged to perform an arithmetic operation on an input operand value comprising a plurality of portions, by performing an independent arithmetic operation on each of the plurality of portions, in order to produce a result value comprising a plurality of result portions. Storage circuitry is arranged to store the result value within a selected lane of the plurality of lanes, such that each result portion is stored in a different vector data storage element within the corresponding section for the selected lane. Such an approach allows efficient processing of input operand values in a manner that is not constrained by the size of the vector data storage elements, and in particular in a way that is vector length agnostic.

公开(公告)号：US20180157464A1

公开(公告)日：2018-06-07

申请号：US15370660

申请日：2016-12-06

申请人： ARM Limited

发明人： David Raymond LUTZ ,  Neil BURGESS ,  Christopher Neal HINDS ,  Andreas Due ENGH-HALSTVEDT

IPC分类号： G06F7/483 ,  G06F7/499

CPC分类号： G06F7/483 ,  G06F7/49915 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30025 ,  G06F9/30036

摘要： An apparatus and method are provided for performing arithmetic operations to accumulate floating-point numbers. The apparatus comprises execution circuitry to perform arithmetic operations, and decoder circuitry to decode a sequence of instructions in order to generate control signals to control the arithmetic operations performed by the execution circuitry. A convert and accumulate instruction is provided, and the decoder circuitry is responsive to decoding such a convert and accumulate instruction within the sequence of instructions to generate one or more control signals to control the execution circuitry. In particular, the execution circuitry is responsive to such control signals to convert at least one floating-point operand identified by the convert and accumulate instruction into a corresponding N-bit fixed-point operand having M fraction bits, where M is less than N and M is dependent on a format of the floating-point operand. In addition, the execution circuitry accumulates each corresponding N bit fixed-point operand and a P bit fixed-point operand identified by the convert and accumulate instruction in order to generate a P bit fixed-point result value, where P is greater than N and also has M fraction bits. This provides a fast and efficient mechanism for accumulating floating-point numbers in a manner that is associative, and hence enables reproducible and correct results to be generated irrespective of the order in which the floating-point numbers are accumulated.

公开(公告)号：US20170351488A1

公开(公告)日：2017-12-07

申请号：US15169996

申请日：2016-06-01

申请人： ARM LIMITED

发明人： Christopher Neal HINDS ,  David Raymond LUTZ

IPC分类号： G06F7/485

CPC分类号： G06F7/485 ,  G06F7/48

摘要： Apparatus and a corresponding method are disclosed relating to circuitry to perform an arithmetic operation on one or more input operands, where the circuitry is responsive to an equivalence of a result value of the arithmetic operation with at least one of the one or more input operands, when the one or more input operands are not an identity element for the arithmetic operation, to generate a signal indicative of the equivalence. Idempotency (between at least one input operand and the result value) is thus identified.

公开(公告)号：US20170102939A1

公开(公告)日：2017-04-13

申请号：US14877003

申请日：2015-10-07

申请人： ARM LIMITED

发明人： David Raymond LUTZ ,  Christopher Neal HINDS ,  Neil BURGESS

IPC分类号： G06F9/30 ,  G06F7/483

CPC分类号： G06F9/3001 ,  G06F7/483 ,  G06F7/49947 ,  G06F9/30 ,  G06F9/3016

摘要： Processing circuitry 2 supports execution of program instructions having a rounding position input operand so as to generate control signals 14 for controlling processing circuitry 16 to process a floating point input operand with a significand value to generate an output result which depends upon a value from rounding the floating point input operand using a variable rounding point within the significand of the floating point input operand as specified by the rounding position input operand. In this way, processing operations having as inputs floating point operands and anchored number operands may be facilitated.

公开(公告)号：US20170090868A1

公开(公告)日：2017-03-30

申请号：US14865342

申请日：2015-09-25

申请人： ARM LIMITED

发明人： David Raymond LUTZ

IPC分类号： G06F7/487 ,  G06F5/01

CPC分类号： G06F7/487 ,  G06F5/012

摘要： An apparatus and method for floating-point multiplication are provided. Two partial products are generated from two operand significands. An unbiased result exponent is determined from operand exponent values and leading zero counts, and a shift amount and direction for a product significand as needed for a predetermined minimum exponent value of a predetermined canonical format. First and second rounding values for injection into addition of the partial products are generated by shifting a predetermined rounding pattern by the shift amount in an opposite shift direction for the first rounding value and left shifting by one bit the first rounding value to give the second. The first and second partial products are added together with the first rounding value to give a first product significand, and are added together with the second rounding value to give a second product significand. These product significands are shifted by the shift amount in the shift direction and one is then selected in order to generate a formatted significand in the predetermined canonical format. The early injection rounding provides a faster floating-point multiplier.

公开(公告)号：US20160179469A1

公开(公告)日：2016-06-23

申请号：US14579435

申请日：2014-12-22

申请人： ARM Limited

发明人： Neil BURGESS ,  David Raymond LUTZ

IPC分类号： G06F7/509

CPC分类号： G06F7/509 ,  G06F7/544 ,  G06F2207/5442

摘要： An apparatus comprises processing circuitry for performing an absolute difference operation for generating an absolute difference value in response to the first operand the second operand. The processing circuitry supports variable data element sizes for data elements of the first and second operands and the absolute difference value. Each data element of the absolute difference value represents an absolute difference between corresponding data elements of the first and second operands. The processing circuitry has an adding stage for performing at least one addition to generate at least one intermediate value and an inverting stage for inverting selected bits of each intermediate value. Control circuitry generates control information based on the current data element size and status information generated in the adding stage, to identify the selected bits to be inverted in the inverting stage to convert each intermediate value into a corresponding portion of the absolute difference value.

摘要翻译： 一种装置包括处理电路，用于执行绝对差分运算，以响应于第一操作数和第二操作数产生绝对差值。 处理电路支持用于第一和第二操作数的数据元素和绝对差值的可变数据元素大小。 绝对差值的每个数据元素表示第一和第二操作数的相应数据元素之间的绝对差。 处理电路具有用于执行至少一个加法以生成至少一个中间值的加法阶段和用于反转每个中间值的所选位的反相级。 控制电路基于当前数据元素大小和在加法阶段中生成的状态信息来生成控制信息，以识别在反相级中要反相的选定位，以将每个中间值转换成绝对差值的对应部分。

公开(公告)号：US20160147503A1

公开(公告)日：2016-05-26

申请号：US14549639

申请日：2014-11-21

申请人： ARM LIMITED

发明人： Neil BURGESS ,  David Raymond LUTZ

IPC分类号： G06F7/535 ,  G06F7/552 ,  G06F9/30

CPC分类号： G06F7/535 ,  G06F7/5375 ,  G06F7/5525 ,  G06F9/3001 ,  G06F2207/5351 ,  G06F2207/5528

摘要： A processing apparatus has combined divide-square root circuitry for performing a radix-N SRT divide algorithm and a radix-N SRT square root algorithm, where N is an integer power-of-2. The combined circuitry has shared remainder updating circuitry which performs remainder updates for a greater number of iterations per cycle for the SRT divide algorithm than for the SRT square root algorithm. This allows reduced circuit area while avoiding the SRT square root algorithm compromising the performance of the SRT divide algorithm.

摘要翻译： 处理装置具有用于执行基数-N SRT除法算法和基数N SRT平方根算法的组合的分方根电路，其中N是2的整数幂。 组合电路具有共享余数更新电路，对于SRT除法算法而言，对于SRT平方根算法，每个周期执行更多次迭代的余数更新。 这允许减小电路面积，同时避免SRT平方根算法损害SRT除法算法的性能。