公开(公告)号：US09122890B2

公开(公告)日：2015-09-01

申请号：US14019580

申请日：2013-09-06

Applicant: ARM LIMITED

Inventor： Thomas Christopher Grocutt ,  Stuart David Biles ,  Simon John Craske

IPC: G06F21/00 ,  G06F21/62 ,  G06F21/50 ,  G06F21/52 ,  G06F21/54 ,  G06F21/55

CPC classification number: G06F21/629 ,  G06F21/50 ,  G06F21/52 ,  G06F21/54 ,  G06F21/554 ,  G06F21/74 ,  G06F2221/2105

Abstract: A data processing apparatus including processing circuitry having a secure domain and a further different secure domain and a data store for storing data and instructions. The data store includes a plurality of regions each corresponding to a domain, and at least one secure region for storing sensitive data accessible by the data processing circuitry operating in the secure domain and not accessible by the data processing circuitry operating in the further different secure domain and a less secure region for storing less sensitive data. The processing circuitry is configured to verify that a region of the data store storing the program instruction corresponds to a current domain of operation of the processing circuitry and, if not, to verify whether the program instruction includes a guard instruction and, if so, to switch to the domain corresponding to the region of the data store storing the program instruction.

Abstract translation: 一种数据处理装置，包括具有安全域和另一不同安全域的处理电路以及用于存储数据和指令的数据存储。 数据存储器包括多个区域，每个区域各自对应于域，以及至少一个安全区域，用于存储由安全域中操作的数据处理电路可访问的敏感数据，并且不能由在另外不同的安全域中操作的数据处理电路访问 以及用于存储较不敏感数据的较不安全的区域。 处理电路被配置为验证存储程序指令的数据存储区域对应于处理电路的当前操作区域，如果不是，则验证程序指令是否包括保护指令，并且如果是，则 切换到与存储程序指令的数据存储区域对应的域。

公开(公告)号：US11755243B2

公开(公告)日：2023-09-12

申请号：US17056944

申请日：2019-05-02

Applicant: Arm Limited

Inventor： Simon John Craske

IPC: G06F3/06 ,  G06F11/10

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0673 ,  G06F11/1076

Abstract: An apparatus and method are provided for triggering action performance. One example apparatus comprises memory access circuitry to retrieve a data value from a memory location of a memory. The apparatus further comprises action triggering circuitry to determine whether the data value is to be interpreted according to a first interpretation or a second interpretation and, when it is determined that the data value is to be interpreted according to the second interpretation, determine whether the data value defines an action to be performed. When it is determined that the data value defines an action to be performed, the action triggering circuitry is to trigger performance of the action.

公开(公告)号：US11379237B2

公开(公告)日：2022-07-05

申请号：US15572678

申请日：2016-04-07

Applicant: ARM LIMITED

Inventor： Simon John Craske

IPC: G06F9/30 ,  G06F9/38 ,  G06F11/34 ,  G06F1/3296 ,  G06F11/30

Abstract: A data processing apparatus (2) operates in a first mode of operation having a first set of processing circuitry (8, 12, 18, 20, 22) ready to perform processing operations and in a second mode of operation having a second set of processing circuitry (8, 12, 14, 18, 20, 22, 24) ready to perform processing operations. A first proper subset (32) of program instructions within the instruction set supported are processed by the processor using a selectable one of the first mode and the second mode. A second proper subset (34) of program instructions within the instruction set are required to be processed by the processor operating in the second mode. Processing circuitry (14, 24) which is inactive in a mode of operation may be placed into a low power state.

公开(公告)号：US11314641B2

公开(公告)日：2022-04-26

申请号：US15741830

申请日：2016-06-14

Applicant: ARM LIMITED

Inventor： Simon John Craske

IPC: G06F12/06 ,  G06F9/35 ,  G06F12/14 ,  G06F9/30

Abstract: An apparatus (2) comprises one or more bounded pointer storage element (60s) each to store a pointer (62) having associated range information (64) indicating an allowable range of addresses for the pointer (62). Processing circuitry (4) performs, in response to a first type of instruction (70) identifying a given bounded pointer storage element, a predetermined operation for a target range of addresses determined at least in part on the basis of the range information (64) associated with the pointer stored in the given bounded pointer storage element (60).

公开(公告)号：US11256569B2

公开(公告)日：2022-02-22

申请号：US16732465

申请日：2020-01-02

Applicant: Arm Limited

Inventor： Mark Gerald LaVine ,  Simon John Craske

IPC: G06F11/10 ,  G11C29/36

Abstract: A data processing apparatus is provided, which includes storage circuitry comprising a plurality of lines, each of the plurality of lines comprising a data value. Access circuitry accesses a pair of the plurality of lines at a time, the pair of the plurality of lines comprising a further data value, distinct from the data value, and a plurality of error bits to detect or correct errors in the data value in each line in the pair of the plurality of lines.

公开(公告)号：US10997076B2

公开(公告)日：2021-05-04

申请号：US15780726

申请日：2016-09-14

Applicant: ARM LIMITED

Inventor： Antony John Penton ,  Simon John Craske

IPC: G06F12/00 ,  G06F12/084 ,  G06F12/0815 ,  G06F11/00 ,  G06F12/0808 ,  G06F12/0842 ,  G06F12/0831 ,  G06F11/20

Abstract: An apparatus has first processing circuitry and second processing circuity. The second processing circuitry has at least one hardware mechanism providing a greater level of fault protection or fault detection than is provided for the first processing circuitry. Coherency control circuitry controls access to data from at least part of a shared address space by the first and second processing circuitry according to an asymmetric coherency protocol in which a local-only update of data in a local cache of the first processing circuitry is restricted in comparison to a local-only update of data in a local cache of the second processing circuitry.

公开(公告)号：US10747536B2

公开(公告)日：2020-08-18

申请号：US16080736

申请日：2017-03-21

Applicant: ARM LIMITED

Inventor： Alasdair Grant ,  Thomas Christopher Grocutt ,  Simon John Craske

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/32

Abstract: A data processing system provides a loop-end instruction for use at the end of a program loop body specifying an address of a beginning instruction of said program loop body. Loop control circuitry (1000) serves to control repeated execution of the program loop body upon second and subsequent passes through the program loop body using loop control data provided by the loop-end instruction without requiring the loop-end instruction to be explicitly executed upon each pass.

公开(公告)号：US10705587B2

公开(公告)日：2020-07-07

申请号：US15133329

申请日：2016-04-20

Applicant: ARM LIMITED

Inventor： Peter Richard Greenhalgh ,  Simon John Craske ,  Ian Michael Caulfield ,  Max John Batley ,  Allan John Skillman ,  Antony John Penton

IPC: G06F9/38 ,  G06F1/3206 ,  G06F1/3287 ,  G06F9/30 ,  G06F1/3234 ,  G06F1/3237

Abstract: Apparatus for processing data is provided with fetch circuitry for fetching program instructions for execution from one or more active threads of instructions having respective program counter values. Pipeline circuitry has a first operating mode and a second operating mode. Mode switching circuitry switches the pipeline circuitry, between the first operating mode and the second operating mode in dependence upon a number of active threads of program instructions having program instructions available to be executed. The first operating mode has a lower average energy consumption per instruction executed than the second operating mode and the second operating mode has a higher average rate of instruction execution for a single thread than the first operating mode. The first operating mode may utilise a barrel processing pipeline to perform interleaved multiple thread processing. The second operating mode may utilise an out-of-order processing pipeline for performing out-of-order processing.

公开(公告)号：US10409721B2

公开(公告)日：2019-09-10

申请号：US15681467

申请日：2017-08-21

Applicant: ARM LIMITED

Inventor： Simon John Craske

IPC: G06F5/10 ,  G06F7/02 ,  G06F12/02 ,  G06F7/509 ,  G06F17/50

Abstract: Comparator circuitry comprises carry-save-addition (CSA) circuitry to generate a set of partial sum bits and a set of carry bits in respect of corresponding bit positions in a first input value, a second input value, a carry-in value associated with the first and second input values, and a third input value, the CSA circuitry comprising inverter circuitry to provide a relative inversion between the third input value and the group consisting of the first and second input values; and combiner circuitry to combine the set of partial sum bits, the set of carry bits offset by a predetermined number of bits in a more significant bit direction, the carry-in value and 1, to generate at least a carry output bit; in which the carry output bit is indicative of whether the third input value is greater than the sum of the first and second input values.

公开(公告)号：US10140476B2

公开(公告)日：2018-11-27

申请号：US15189284

申请日：2016-06-22

Applicant: ARM LIMITED

Inventor： John Michael Horley ,  Michael John Williams ,  Simon John Craske ,  Uma Maheswari Ramalingam

IPC: G06F21/74

Abstract: A data processing apparatus comprises a processing element having associated memory storage and one or more registers, the processing element being configured to perform processing activities in two or more security modes so as to inhibit a processing activity performed in one of the security modes from accessing at least some information associated with a processing activity performed in another of the security modes; in which the processing element is configured, in response to a function call causing a branch from a processing activity in a first security mode to a processing activity in a second security mode, to store the contents of one or more of the registers in the memory storage and, in response to a branch return to the first security mode, to retrieve the register contents from the memory storage; and trace apparatus configured to generate items of trace data indicative of processing activities of the processing element; in which the trace apparatus is configured to detect a branch return operation by the processing element and to generate one or more items of trace data relating to the branch return operation; and in which the trace apparatus is configured to detect the processing element retrieving register contents from the memory storage in response to a branch return to the first security mode and to generate one or more further items of trace data relating to the retrieval of the register contents from the memory storage.