公开(公告)号：US20150355275A1

公开(公告)日：2015-12-10

申请号：US14680425

申请日：2015-04-07

Applicant: ARM LIMITED

Inventor： Mark Gerald LaVine

IPC: G01R31/3177

CPC classification number: G01R31/3177

Abstract: A logic analyzer 6 is provided with a state controller 12 and analyzer circuitry. The logic analyzer switches between a programmable sequence of trigger states and generates an index signal within each trigger state. The index signal is used to control the analyzer circuitry to select appropriate portions of programmable trigger state data so as to configure the matching operation performed against hardware signal values taken from hardware circuitry 4 which is subject to analysis by the logic analyzer 6.

Abstract translation: 逻辑分析器6设置有状态控制器12和分析器电路。 逻辑分析仪在可编程触发状态序列之间切换，并在每个触发状态下生成一个索引信号。 索引信号用于控制分析器电路以选择可编程触发状态数据的适当部分，以配置对硬件信号值执行的匹配操作，硬件信号值取决于由逻辑分析仪6进行分析的硬件电路4。

公开(公告)号：US09897652B2

公开(公告)日：2018-02-20

申请号：US14680425

申请日：2015-04-07

Applicant: ARM LIMITED

Inventor： Mark Gerald LaVine

IPC: G06F11/00 ,  G01R31/3177

CPC classification number: G01R31/3177

Abstract: A logic analyzer 6 is provided with a state controller 12 and analyzer circuitry. The logic analyzer switches between a programmable sequence of trigger states and generates an index signal within each trigger state. The index signal is used to control the analyzer circuitry to select appropriate portions of programmable trigger state data so as to configure the matching operation performed against hardware signal values taken from hardware circuitry 4 which is subject to analysis by the logic analyzer 6.

公开(公告)号：US10311963B2

公开(公告)日：2019-06-04

申请号：US15491239

申请日：2017-04-19

Applicant: ARM LIMITED

Inventor： Mark Gerald LaVine ,  Alan Jeremy Becker

IPC: G11C29/00 ,  G11C29/12 ,  G06F3/06 ,  G11C29/38 ,  G11C29/44 ,  G11C7/10 ,  G11C8/06 ,  G11C8/10 ,  G11C7/22 ,  G11C29/04

Abstract: A data processing apparatus comprises at least one memory configured to store data; processing circuitry to access data in the at least one memory. Memory built-in self-test (MBIST) circuitry has an interface to access the at least one memory and is configured to perform a test procedure for testing at least one target memory location of the at least one memory. The test procedure involves at least writing test data to the target memory location. Diagnostic circuitry executes a diagnostic procedure to generate diagnostic data in response to processing operations carried out by the processing circuitry. The MBIST circuitry is configured to control writing of the diagnostic data generated by the diagnostic circuitry to memory locations in a temporarily reserved memory region comprising at least a portion of the at least one memory.

公开(公告)号：US10061671B2

公开(公告)日：2018-08-28

申请号：US14684558

申请日：2015-04-13

Applicant: ARM Limited

Inventor： Mark Gerald LaVine

IPC: G06F11/27 ,  G06F11/25 ,  G06F11/273 ,  G06F11/34 ,  G01R31/3177 ,  G06F11/30

Abstract: Apparatus comprising logic analyzer circuitry comprises a succession of two or more successive trigger condition detectors each configured to detect a match between a respective trigger condition and data handling activity relating to data handling transactions each having a respective transaction identifier; the succession of trigger condition detectors being configured so that a detection by a trigger condition detector of a match with its respective trigger condition enables a next trigger condition detector in the succession to initiate detection of a match with the respective trigger condition of that next trigger condition detector; and a transaction identifier detector associated with a first trigger condition detector in the succession, configured to detect the transaction identifier relating to a data handling transaction for which a match is detected by the first trigger condition detector, and to supply the detected transaction identifier to a subsequent trigger condition detector in the succession of trigger condition detectors; in which the subsequent trigger condition detector is configured to apply the detected transaction identifier as at least a part of its respective trigger condition so as to detect a match only in respect of a data handling transaction having that transaction identifier.

公开(公告)号：US20240244008A1

公开(公告)日：2024-07-18

申请号：US18096314

申请日：2023-01-12

Applicant: Arm Limited

Inventor： Apurva Patel ,  Ashok Kumar Tummala ,  Ranjini Mysore Nagaraju ,  Mark Gerald LaVine

IPC: H04L47/35 ,  H04L43/0882 ,  H04L47/28 ,  H04L49/90

CPC classification number: H04L47/35 ,  H04L43/0882 ,  H04L47/28 ,  H04L49/90

Abstract: A mechanism is provided efficient packing of network flits in a data processing network. Transaction messages for transmission across a communication link of a data processing network are analyzed to determine a group of transaction messages to be passed to a packing logic block for increased packing efficiency. The transaction messages are packed into slots of one or more network flits and transmitted across a communication link. The mechanism reduces the number of unused slots in a transmitted network.

公开(公告)号：US11256569B2

公开(公告)日：2022-02-22

申请号：US16732465

申请日：2020-01-02

Applicant: Arm Limited

Inventor： Mark Gerald LaVine ,  Simon John Craske

IPC: G06F11/10 ,  G11C29/36

Abstract: A data processing apparatus is provided, which includes storage circuitry comprising a plurality of lines, each of the plurality of lines comprising a data value. Access circuitry accesses a pair of the plurality of lines at a time, the pair of the plurality of lines comprising a further data value, distinct from the data value, and a plurality of error bits to detect or correct errors in the data value in each line in the pair of the plurality of lines.

公开(公告)号：US20160299825A1

公开(公告)日：2016-10-13

申请号：US14684558

申请日：2015-04-13

Applicant: ARM Limited

Inventor： Mark Gerald LaVine

IPC: G06F11/25 ,  G06F11/34 ,  G06F11/30

CPC classification number: G06F11/25 ,  G01R31/3177 ,  G06F11/27 ,  G06F11/273 ,  G06F11/3089 ,  G06F11/3471 ,  G06F2201/87

Abstract: Apparatus comprising logic analyser circuitry comprises a succession of two or more successive trigger condition detectors each configured to detect a match between a respective trigger condition and data handling activity relating to data handling transactions each having a respective transaction identifier; the succession of trigger condition detectors being configured so that a detection by a trigger condition detector of a match with its respective trigger condition enables a next trigger condition detector in the succession to initiate detection of a match with the respective trigger condition of that next trigger condition detector; and a transaction identifier detector associated with a first trigger condition detector in the succession, configured to detect the transaction identifier relating to a data handling transaction for which a match is detected by the first trigger condition detector, and to supply the detected transaction identifier to a subsequent trigger condition detector in the succession of trigger condition detectors; in which the subsequent trigger condition detector is configured to apply the detected transaction identifier as at least a part of its respective trigger condition so as to detect a match only in respect of a data handling transaction having that transaction identifier.

Abstract translation: 包括逻辑分析器电路的装置包括一系列两个或多个连续的触发条件检测器，每个触发条件检测器被配置为检测相应的触发条件和与每个具有相应的交易标识符的数据处理事务相关的数据处理活动之间的匹 触发条件检测器的连续配置使得触发条件检测器与其相应的触发条件匹配的检测使得下一个触发条件检测器能够先后地启动与下一个触发条件的相应触发条件的匹配检测 探测器; 以及与所述连续中的第一触发条件检测器相关联的交易标识符检测器，被配置为检测与由所述第一触发条件检测器检测到匹配的数据处理交易相关的交易标识符，并将检测到的交易标识符提供给 触发条件检测器后续触发条件检测器; 其中随后的触发条件检测器被配置为将检测到的事务标识符应用于其相应触发条件的至少一部分，以便仅针对具有该事务标识符的数据处理事务来检测匹配。