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公开(公告)号：US11481384B2
公开(公告)日：2022-10-25
申请号：US16094224
申请日：2017-03-29
Applicant: ARM LIMITED
Inventor： Graeme Peter Barnes , Stuart David Biles
Abstract: An apparatus is provided comprising storage elements to store data blocks, where each data block has capability metadata associated therewith identifying whether the data block specifies a capability, at least one capability type being a bounded pointer. Processing circuitry is then arranged to be responsive to a bulk capability metadata operation identifying a plurality of the storage elements, to perform an operation on the capability metadata associated with each data block stored in the plurality of storage elements. Via a single specified operation, this hence enables query and/or modification operations to be performed on multiple items of capability metadata, hence providing more efficient access to such capability metadata.
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公开(公告)号：US08966282B2
公开(公告)日：2015-02-24
申请号：US13627209
申请日：2012-09-26
Applicant: ARM Limited
CPC classification number: G06F21/602 , G06F9/30007 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30145 , G06F9/3887 , G09C1/00 , H04L9/0643 , H04L9/3239 , H04L2209/12 , H04L2209/125
Abstract: A data processing system 2 includes a single instruction multiple data register file 12 and single instruction multiple processing circuitry 14. The single instruction multiple data processing circuitry 14 supports execution of cryptographic processing instructions for performing parts of a hash algorithm. The operands are stored within the single instruction multiple data register file 12. The cryptographic support instructions do not follow normal lane-based processing and generate output operands in which the different portions of the output operand depend upon multiple different elements within the input operand.
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公开(公告)号：US11119925B2
公开(公告)日：2021-09-14
申请号：US16609298
申请日：2018-04-19
Applicant: Arm Limited
Inventor： Stuart David Biles , Graeme Peter Barnes
IPC: G06F12/0815 , G06F16/907 , G06F9/38 , G06F9/46 , G06F12/0811
Abstract: Apparatus comprising cache storage and a method of operating such a cache storage are provided. Data blocks in the cache storage have capability metadata stored in association therewith identifying whether the data block specifies a capability or a data value. At least one type of capability is a bounded pointer. Responsive to a write to a data block in the cache storage a capability metadata modification marker is set in association with the data block, indicative of whether the capability metadata associated with the data block has changed since the data block was stored in the cache storage. This supports the security of the system, such that modification of the use of a data block from a data value to a capability cannot take place unless intended. Efficiencies may also result when capability metadata is stored separately from other data in memory, as fewer accesses to memory can be made.
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公开(公告)号：US20150154045A1
公开(公告)日：2015-06-04
申请号：US14618211
申请日：2015-02-10
Applicant: ARM Limited , The Regents of the University of Michigan
Inventor： Geoffrey Blake , Trevor Nigel Mudge , Nathan Yong Seng Chong , Ronald George Dreslinski , Stuart David Biles , Emre Özer
CPC classification number: G06F9/467 , G06F9/30087 , G06F9/466 , G06F12/084 , G06F12/0875 , G06F2212/452 , G06F2212/621
Abstract: A hardware transactional memory is provided within a multiprocessor system with coherency control and hardware transaction memory control circuitry that serves to at least partially manage the scheduling of processing transactions in dependence upon conflict data. The conflict data characterizes previously encountered conflicts between processing transactions. The scheduling is performed such that a candidate processing transaction will not be scheduled if the conflict data indicates that one of the already running processing transactions has previously conflicted with the candidate processing transaction.
Abstract translation: 在具有相关性控制和硬件事务存储器控制电路的多处理器系统内提供硬件事务存储器，其用于至少部分地根据冲突数据管理处理事务的调度。 冲突数据表示处理事务之前遇到的冲突。 执行调度，使得如果冲突数据指示已经运行的处理事务中的一个先前与候选处理事务冲突，则候选处理事务将不被调度。
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公开(公告)号：US09703966B2
公开(公告)日：2017-07-11
申请号：US14792796
申请日：2015-07-07
Applicant: ARM Limited
CPC classification number: G06F21/602 , G06F9/30007 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30145 , G06F9/3887 , G09C1/00 , H04L9/0643 , H04L9/3239 , H04L2209/12 , H04L2209/125
Abstract: A data processing system includes a single instruction multiple data register file and single instruction multiple processing circuitry. The single instruction multiple data processing circuitry supports execution of cryptographic processing instructions for performing parts of a hash algorithm. The operands are stored within the single instruction multiple data register file. The cryptographic support instructions do not follow normal lane-based processing and generate output operands in which the different portions of the output operand depend upon multiple different elements within the input operand.
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Patent Agency Ranking
6.发明授权Data processing apparatus and method for analysing transient faults occurring within storage elements of the data processing apparatus 有权用于分析数据处理装置的存储元件内发生的瞬态故障的数据处理装置和方法公开(公告)号：US09116844B2
公开(公告)日：2015-08-25
申请号：US14246162
申请日：2014-04-07
Applicant: ARM Limited
Inventor： Emre Ozer , Yiannakis Sazeides , Daniel Kershaw , Stuart David Biles
CPC classification number: G06F11/1415 , G06F11/0727 , G06F11/076 , G06F11/0787 , G06F2201/86
Abstract: A data processing apparatus has a plurality of storage elements residing at different physical locations within the apparatus, and fault history circuitry for detecting local transient faults occurring in each storage element, and for maintaining global transient fault history data based on the detected local transient faults. Analysis circuitry monitors the global transient fault history data to determine, based on predetermined criteria, whether the global transient fault history data is indicative of random transient faults occurring within the data processing apparatus, or is indicative of a coordinated transient fault attack. The analysis circuitry is then configured to initiate a countermeasure action on determination of a coordinated transient fault attack. This provides a simple and effective mechanism for distinguishing between random transient faults that may naturally occur, and a coordinated transient fault attack that may be initiated in an attempt to circumvent the security of the data processing apparatus.
Abstract translation: 数据处理装置具有驻留在装置内的不同物理位置的多个存储元件，以及故障历史电路，用于检测每个存储元件中发生的局部瞬态故障，并且用于基于检测到的局部瞬态故障来维护全局瞬态故障历史数据。 分析电路监视全局瞬态故障历史数据，以基于预定标准确定全局瞬态故障历史数据是否表示在数据处理装置内发生的随机瞬态故障，或指示协调的瞬时故障攻击。 分析电路然后被配置为启动对协调的瞬态故障攻击的确定的对策动作。 这提供了一种用于区分可能自然发生的随机瞬态故障的简单和有效的机制，以及可以在试图绕过数据处理设备的安全性时发起的协调的瞬态故障攻击。
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公开(公告)号：US09104400B2
公开(公告)日：2015-08-11
申请号：US14585900
申请日：2014-12-30
Applicant: ARM LIMITED
CPC classification number: G06F21/602 , G06F9/30007 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30145 , G06F9/3887 , G09C1/00 , H04L9/0643 , H04L9/3239 , H04L2209/12 , H04L2209/125
Abstract: A data processing system 2 includes a single instruction multiple data register file 12 and single instruction multiple processing circuitry 14. The single instruction multiple data processing circuitry 14 supports execution of cryptographic processing instructions for performing parts of a hash algorithm. The operands are stored within the single instruction multiple data register file 12. The cryptographic support instructions do not follow normal lane-based processing and generate output operands in which the different portions of the output operand depend upon multiple different elements within the input operand.
Abstract translation: 数据处理系统2包括单指令多数据寄存器文件12和单指令多处理电路14.单指令多数据处理电路14支持执行用于执行散列算法部分的密码处理指令。 操作数存储在单指令多数据寄存器文件12中。加密支持指令不遵循正常的基于通道的处理，并且生成输出操作数，其中输出操作数的不同部分取决于输入操作数中的多个不同元素。
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公开(公告)号：US08898430B2
公开(公告)日：2014-11-25
申请号：US13705316
申请日：2012-12-05
Applicant: ARM Limited
Inventor： Viswanath Chakrala , Timothy Nicholas Hay , Stuart David Biles
CPC classification number: G06F12/0891 , G06F11/073 , G06F11/0793
Abstract: A data processing apparatus having a memory configured to store tables having virtual to physical address translations, a cache configured to store a subset of the virtual to physical address translations and cache management circuitry configured to control transactions received from the processor requesting virtual address to physical address translations. The data processing apparatus identifies where a faulting transaction has occurred during execution of a context and whether the faulting transaction has a transaction stall or transaction terminate fault. The cache management circuitry is responsive to identification of the faulting transaction having a transaction terminate fault to invalidate all address translations in the cache that relate to the context of the faulting transaction such that a valid bit associated with each entry in the cache is set to invalid for the address translations.
Abstract translation: 一种具有被配置为存储具有虚拟到物理地址转换的表的存储器的数据处理装置，被配置为存储虚拟到物理地址转换的子集的高速缓存以及被配置为控制从处理器接收到的处理器请求虚拟地址到物理地址的高速缓存管理电路 翻译。 数据处理装置识别在执行上下文期间发生故障事务的位置，以及故障事务是否具有事务处理或事务终止故障。 高速缓存管理电路响应于具有事务终止故障的故障事务的识别，以使与高速缓存中的上下文相关的高速缓存中的所有地址转换无效，使得与高速缓存中的每个条目相关联的有效位被设置为无效 为地址翻译。
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公开(公告)号：US20140156949A1
公开(公告)日：2014-06-05
申请号：US13705316
申请日：2012-12-05
Applicant: ARM LIMITED
Inventor： Viswanath CHAKRALA , Timothy Nicholas Hay , Stuart David Biles
IPC: G06F12/08
CPC classification number: G06F12/0891 , G06F11/073 , G06F11/0793
Abstract: A data processing apparatus having a memory configured to store tables having virtual to physical address translations, a cache configured to store a subset of the virtual to physical address translations and cache management circuitry configured to control transactions received from the processor requesting virtual address to physical address translations. The data processing apparatus identifies where a faulting transaction has occurred during execution of a context and whether the faulting transaction has a transaction stall or transaction terminate fault. The cache management circuitry is responsive to identification of the faulting transaction having a transaction terminate fault to invalidate all address translations in the cache that relate to the context of the faulting transaction such that a valid bit associated with each entry in the cache is set to invalid for the address translations.
Abstract translation: 一种具有被配置为存储具有虚拟到物理地址转换的表的存储器的数据处理装置，被配置为存储虚拟到物理地址转换的子集的高速缓存以及被配置为控制从处理器接收到的处理器请求虚拟地址到物理地址的高速缓存管理电路 翻译。 数据处理装置识别在执行上下文期间发生故障事务的位置，以及故障事务是否具有事务处理或事务终止故障。 高速缓存管理电路响应于具有事务终止故障的故障事务的识别，以使与高速缓存中的上下文相关的高速缓存中的所有地址转换无效，使得与高速缓存中的每个条目相关联的有效位被设置为无效 为地址翻译。
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10.发明授权公开(公告)号：US10241933B2
公开(公告)日：2019-03-26
申请号：US15123805
申请日：2015-03-04
Applicant: ARM LIMITED
Abstract: An asymmetric multiprocessor system includes a plurality of processor cores supporting transactional memory via controllers as well as one or more processor cores which do not support transactional memory via hardware. The controllers respond to receipt of a request for exclusive access to a lock address by determining whether or not their associated processors is currently executing a memory transaction guarded by a lock value stored at that lock address and if their processor is executing such a transaction, then delaying releasing the lock address for exclusive access until a predetermined condition is met. If the processor is not executing such a guarded memory transaction, then the lock address may be unconditionally released for exclusive access. The predetermined condition may be that a threshold delay has been exceeded since the request was received and/or that the request has previously been received and refused a threshold number of times. The request may arise through execution of a transaction start instruction which serves to read a lock address from an architectural register storing the lock address should the processor executing that transaction start instruction not already be executing a pending memory transaction. If the processor is already executing a memory transaction, then the transaction start instruction need not access the lock value stored at the lock address held within the lock address register as it may be assumed that the lock value has already been checked.
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