公开(公告)号：US12087357B2

公开(公告)日：2024-09-10

申请号：US17844551

申请日：2022-06-20

Applicant: Arm Limited

Inventor： Yew Keong Chong ,  Sriram Thyagarajan ,  Andy Wangkun Chen ,  Arjun Singh ,  Ayush Kulshrestha

IPC: G11C11/412 ,  G11C11/419

CPC classification number: G11C11/419 ,  G11C11/412

Abstract: Various implementations described herein are directed to a device having memory circuitry having multi-port bitcells, wherein each bitcell of the multi-port bitcells has a read-write port and a read port. The device may have read-write circuitry coupled to the read-write port, wherein the read-write circuitry has write-drive logic and read-sense logic that provide for at least one write and at least one read in a single clock cycle.

公开(公告)号：US12066855B2

公开(公告)日：2024-08-20

申请号：US18091719

申请日：2022-12-30

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Yew Keong Chong ,  Sriram Thyagarajan ,  Akash Bangalore Srinivasa ,  Munish Kumar ,  Khushal Gelda ,  Akshay Kumar

IPC: G06F1/00 ,  G06F1/06 ,  G06F1/10 ,  G06F11/30

CPC classification number: G06F1/10 ,  G06F1/06 ,  G06F11/3062

Abstract: Various implementations described herein are related to a device having multi-port circuit architecture with multiple ports. The multi-port circuit architecture may expand a primary clock into multiple dummy clocks so as to separately track, simulate and report clock power consumption for each port of the multiple ports to a central processing unit.

公开(公告)号：US20240233814A9

公开(公告)日：2024-07-11

申请号：US17971226

申请日：2022-10-21

Applicant: Arm Limited

Inventor： Vianney Antoine Choserot ,  Andy Wangkun Chen ,  Yew Keong Chong ,  Sriram Thyagarajan

IPC: G11C11/412 ,  G11C11/418 ,  G11C11/419

CPC classification number: G11C11/412 ,  G11C11/418 ,  G11C11/419

Abstract: Various implementations described herein are related to a device having a storage node with a bitcell. The device may have a first stage that performs a first write based on an internal bitline signal, a first write wordline signal and a second write wordline signal. The first stage outputs the internal bitline signal. The device may have a second stage that receives the internal bitline signal and performs a second write of the internal bitline signal to the bitcell. The device may have a third stage with write wordline ports and write bitline ports. The third stage provides the internal bitline signal based on a selected write wordline signal from a write wordline port of the write wordline ports and based on a selected bitline signal based on a write bitline port of the write bitline ports.

公开(公告)号：US11900995B2

公开(公告)日：2024-02-13

申请号：US17223950

申请日：2021-04-06

Applicant: Arm Limited

Inventor： Rajiv Kumar Sisodia ,  Andy Wangkun Chen ,  Sriram Thyagarajan ,  Yew Keong Chong ,  Ayush Kulshrestha ,  Munish Kumar

IPC: G11C11/419 ,  G11C11/418 ,  G11C11/412

CPC classification number: G11C11/418 ,  G11C11/412 ,  G11C11/419

Abstract: Various implementations described herein are related to a method for accessing a bitcell in an array of bitcells with a wordline and a bitline. The method may perform a precharge operation on the bitline that precharges the bitline after a read cycle and before a write cycle. Also, the method may extend precharge time of the precharge operation between the read cycle and the write cycle, e.g., by modulating a wordline signal on the wordline with early cut-off of the wordline signal on the wordline during the read cycle.

公开(公告)号：US20230410896A1

公开(公告)日：2023-12-21

申请号：US17844551

申请日：2022-06-20

Applicant: Arm Limited

Inventor： Yew Keong Chong ,  Sriram Thyagarajan ,  Andy Wangkun Chen ,  Arjun Singh ,  Ayush Kulshrestha

IPC: G11C11/419 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C11/412

Abstract: Various implementations described herein are directed to a device having memory circuitry having multi-port bitcells, wherein each bitcell of the multi-port bitcells has a read-write port and a read port. The device may have read-write circuitry coupled to the read-write port, wherein the read-write circuitry has write-drive logic and read-sense logic that provide for at least one write and at least one read in a single clock cycle.

公开(公告)号：US11837543B2

公开(公告)日：2023-12-05

申请号：US17006695

申请日：2020-08-28

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Sriram Thyagarajan ,  Yew Keong Chong ,  Sony ,  Ettore Amirante ,  Ayush Kulshrestha

IPC: H01L23/528 ,  H01L27/06

CPC classification number: H01L23/5286 ,  H01L27/0688

Abstract: Various implementations described herein are related to various devices having a frontside power network with frontside supply rails and a backside power network with backside supply rails. The device may include intermixing architecture with transition vias that couple the frontside power network to the backside power network. The intermixing architecture may transition the frontside supply rails of the frontside power network to the backside supply rails of the backside power network.

公开(公告)号：US20220293522A1

公开(公告)日：2022-09-15

申请号：US17199143

申请日：2021-03-11

Applicant: Arm Limited

Inventor： Sriram Thyagarajan ,  Ettore Amirante ,  Andy Wangkun Chen ,  Yew Keong Chong ,  Sony .

IPC: H01L23/528 ,  G06F30/3953 ,  H01L23/522 ,  G06F119/06

Abstract: Various implementations described herein are directed to a method for routing buried power rails underneath a memory instance. The method may identify first rails of the buried power rails disposed in a first layer and second rails of the buried power rails disposed perpendicular to the first rails in a second layer. The method may identify long rails of the first rails with a first length and short rails of the first rails with a second length that is less than the first length. The method may separately couple the long rails and the short rails to the second rails with vias that extend between the first layer and the second layer.

公开(公告)号：US11443777B2

公开(公告)日：2022-09-13

申请号：US17019030

申请日：2020-09-11

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Sriram Thyagarajan ,  Yew Keong Chong ,  Sony ,  Ettore Amirante ,  Ayush Kulshrestha

IPC: G11C7/04 ,  G11C5/14 ,  G11C8/08

Abstract: Various implementations described herein refer to a device having backside power rails including first backside power rails that supply a core voltage to memory logic and second backside power rails that supply a periphery voltage to control logic. In some implementations, at least one first backside power rail may have a rail break that interrupts continuity so as to allow at least one second backside power rail to supply the periphery voltage to the control logic.

公开(公告)号：US11271567B1

公开(公告)日：2022-03-08

申请号：US17013199

申请日：2020-09-04

Applicant: Arm Limited

Inventor： Andy Wangkun Chen ,  Sriram Thyagarajan ,  Yew Keong Chong ,  Sony ,  Ettore Amirante ,  Ayush Kulshrestha

IPC: H03K19/17736 ,  H03K19/1776

Abstract: Various implementations described herein are related to a device with a frontside power network and a backside power network. The frontside power network may include frontside supply rails coupled to logic circuitry, and also, the backside power network may include buried supply rails. Also, at least one buried supply rail of the buried supply rails may be used as a backside signal path for providing at least one critical signal net to the logic circuitry.

公开(公告)号：US20210333320A1

公开(公告)日：2021-10-28

申请号：US16857144

申请日：2020-04-23

Applicant: Arm Limited

Inventor： Sriram Thyagarajan ,  Pratik Ghanshambhai Satasia ,  Yew Keong Chong ,  Andy Wangkun Chen ,  Mouli Rajaram Chollangi

IPC: G01R31/28 ,  G06F30/3312

Abstract: Various implementations described herein are related to a method for constructing integrated circuitry and identifying input signal paths, internal signal paths and output signal paths associated with the integrated circuitry. The method may include generating a timing table for slew-load characterization of the input signal paths, the internal signal paths and the output signal paths. The method may include simulating corner points for the timing table, building diagonal points for the timing table based on the simulated corner points, and building remaining points for the timing table based on the simulated corner points and the diagonal points.