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公开(公告)号：US20190310851A1
公开(公告)日：2019-10-10
申请号：US16081464
申请日：2017-03-21
Applicant: ARM Limited
Inventor： Thomas Christopher GROCUTT
Abstract: A data processing system supports a predicated-loop instruction that controls vectorised execution of a program loop body in respect of a plurality of vector elements. When the number of elements to be processed is not a whole number multiple of the number of lanes of processing supported for that element size, then the predicated-loop instruction controls suppression of processing in one or more lanes not required.
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公开(公告)号：US20190250914A1
公开(公告)日：2019-08-15
申请号：US16314882
申请日：2017-06-15
Applicant: ARM LIMITED
Inventor： Thomas Christopher GROCUTT
CPC classification number: G06F9/3013 , G06F9/30032 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30105 , G06F9/3012 , G06F9/30145 , G06F9/345 , G06F9/3455
Abstract: There is provided an apparatus that includes a set of vector registers, each of the vector registers being arranged to store a vector comprising a plurality of portions. The set of vector registers is logically divided into a plurality of columns, each of the columns being arranged to store a same portion of each vector. The apparatus also includes register access circuitry that comprises a plurality of access blocks. Each access block is arranged to access a portion in a different column when accessing one of the vector registers than when accessing at least one other of the vector registers. The register access circuitry is arranged to simultaneously access portions in any one of: the vector registers and the columns.
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公开(公告)号：US20190079770A1
公开(公告)日：2019-03-14
申请号：US16085053
申请日：2017-03-21
Applicant: ARM Limited
Inventor： Thomas Christopher GROCUTT , Richard Roy GRISENTHWAITE , Simon John CRASKE , François Christopher Jacques BOTMAN , Bradley John SMITH
CPC classification number: G06F9/3806 , G06F9/3005 , G06F9/30054 , G06F9/30145 , G06F9/321 , G06F9/322 , G06F9/34
Abstract: A data processing system provides a branch forward instruction (BF) which has programmable parameters specifying a branch target address to be branched to and a branch point identifying a program instruction following the branch forward instruction which, when reached, is followed by a branch to the branch target address.
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Patent Agency Ranking
公开(公告)号：US20180373898A1
公开(公告)日：2018-12-27
申请号：US15739825
申请日：2016-05-26
Applicant: ARM Limited
Inventor： Thomas Christopher GROCUTT , Simon John CRASKE
Abstract: A data processing apparatus is provided which uses flag circuitry (174) to set an access tracking flag (SFPA) to a first value when the processing circuitry (154) enters a secure mode in association with a function call and to switch the access tracking flag to a second value upon detection of a first access of at least one type to predetermined state data, such as floating point register data, by processing circuitry operating in the secure mode in association with that function call. This access tracking flag may then be used in association with a lazy-protection program instruction (VLSTM) and a lazy-load program instruction (VLLDM) to control whether or not push operations of the state data and restore operations of the state data are performed in order to prevent access in the non-secure mode to that state data.
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公开(公告)号：US20180314526A1
公开(公告)日：2018-11-01
申请号：US15774066
申请日：2016-10-18
Inventor： Thomas Christopher GROCUTT , Sam AINSWORTH , Timothy Martin JONES
IPC: G06F9/38 , G06F12/1027 , G06F12/0875
Abstract: A main processor 4 executes a main program and has an associated cache memory 6. Event detection circuitry 12 detects events consequent upon execution of the main program and indicative of data to be used by the main processor. One or more programmable further processors 16, 18 is triggered to execute a further program by the events detected by the event detection circuitry 12. Prefetch circuitry 28 is responsive to the further program executed by the one or more programmable further processors to trigger prefetching of the data to be used by the main processor to the cache memory.
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公开(公告)号：US20180307486A1
公开(公告)日：2018-10-25
申请号：US15494911
申请日：2017-04-24
Applicant: ARM LIMITED
IPC: G06F9/30
CPC classification number: G06F9/30032 , G06F9/30196
Abstract: An apparatus has processing circuitry comprising multiplier circuitry for performing multiplication on a pair of input operands. In response to a shift instruction specifying at least one shift amount and a source operand comprising at least one data element, the source operand and a shift operand determined in dependence on the shift amount are provided as input operands to the multiplier circuitry and the multiplier circuitry is controlled to perform at least one multiplication which is equivalent to shifting a corresponding data element of the source operand by a number of bits specified by a corresponding shift amount to generate a shift result value.
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公开(公告)号：US20180173497A1
公开(公告)日：2018-06-21
申请号：US15735721
申请日：2016-05-17
Applicant: ARM LIMITED
Inventor： Daryl John STEWART , Thomas Christopher GROCUTT
CPC classification number: G06F7/485 , G06F5/012 , G06F7/49905 , G06F7/4991 , G06F7/49942 , G06F7/5443
Abstract: An apparatus and method are provided for processing floating point values using an intermediate representation which has significand, exponent and shadow sections. A less significant portion of the exponent of the floating point value defines a range of positions within the significand section where the representation of the significand is to be held. The exponent section holds a representation of a more significant portion of the exponent indicating a selected window of multiple contiguous windows spanning a value range of a format of the floating point value. A first portion of the significand section corresponds to the selected window and a second portion corresponds to an overlap into a further window which is adjacent to and lower in the value range. The shadow section holds values for populating the second portion of the significand section when the representation of the significand of the floating point value is moved to a higher window which is adjacent to and higher in the value range than the selected window. The shadow section allows the selected window to be shifted, such that the summation of multiple values produces the same result independent of the order in which the values are summed.
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公开(公告)号：US20150106682A1
公开(公告)日：2015-04-16
申请号：US14462205
申请日：2014-08-18
Applicant: ARM LIMITED
Inventor： Thomas Christopher GROCUTT , Dall George Mathew AMOS
IPC: G06F11/10
CPC classification number: G06F11/1004 , H03M13/09 , H03M13/091 , H04L1/0041 , H04L1/0061
Abstract: Circuitry for providing error check values for indicating errors in data portions within a data stream. The circuitry comprises error detecting code generation circuitry configured to apply an error detecting code algorithm to the data stream and to thereby generate and periodically update a multi-bit check value as the data stream is processed, each update of the multi-bit check value being indicative of the error detecting code generation circuitry receiving a further item of the data stream. An output for periodically outputting a fragment of the multi-bit check value from the error detecting code generation circuitry during the processing of the data stream, the fragments output each corresponding to a data portion of the data stream. Wherein each of the fragment of the multi-bit check value provides a value indicative of an error occurring either in the corresponding portion of the data stream or in an earlier portion of the data stream.
Abstract translation: 用于提供用于指示数据流内的数据部分中的错误的错误检查值的电路。 该电路包括错误检测代码生成电路，该错误检测代码产生电路经配置以将错误检测代码算法应用于数据流，并由此在处理数据流时生成并周期性地更新多位检查值，多位检查值的更新为 指示错误检测代码生成电路接收数据流的另一个项目。 一种输出，用于在数据流的处理期间周期性地从错误检测码产生电路输出多比特校验值的片段，每个与数据流的数据部分相对应的片段输出。 其中，多位检查值的每个片段提供指示在数据流的相应部分或数据流的较早部分中出现的错误的值。
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