公开(公告)号：US06320411B1

公开(公告)日：2001-11-20

申请号：US09443969

申请日：1999-11-19

申请人： David W. Mendel

发明人： David W. Mendel

IPC分类号： H03K19177

CPC分类号： H03K19/17736 ,  H03K19/17728

摘要： A programmable logic device has plural regions of programmable logic and a general-purpose interconnection network for conveying signals to, from, and between the regions. In addition to the general-purpose interconnection network, more direct interconnections are provided from outputs of each region to inputs of one or more other adjacent or nearby regions. At least some of these direct interconnections are preferably multiplexed with more conventional inputs to the other regions so that the input resources required for each region do not become excessive. The invention is particularly useful for devices which perform basic logic using sum-of-products (“Pterm”) logic. However, the invention is also useful in other types of devices such as those which perform basic logic using look-up tables.

公开(公告)号：US06275065B1

公开(公告)日：2001-08-14

申请号：US09479405

申请日：2000-01-06

申请人： David W. Mendel

发明人： David W. Mendel

IPC分类号： H03K19177

CPC分类号： H03K19/17704 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17744

摘要： A logic element for a programmable logic device to implement a lonely register architecture. The logic element includes logic modules (P0-P4) for implementing combinatorial logic and a register (445). The combinatorial and registered paths of a logic element may be utilized at the same time. The logic modules may be programmably coupled to the register. The output of the register may be programmably coupled through an output buffer (515) to an I/O pad (520) of the integrated circuit. The logic modules may bypass the register and directly programmably couple through the output buffer to the I/O pad. A logic module may be used as a shareable expander by programmably coupling the module through to a global interconnect with other logic modules in LABs coupled to the global interconnect.

摘要翻译： 用于可编程逻辑器件实现孤独寄存器架构的逻辑元件。 逻辑元件包括用于实现组合逻辑的逻辑模块（P0-P4）和寄存器（445）。 逻辑元件的组合和注册路径可以同时使用。 逻辑模块可以可编程地耦合到寄存器。 寄存器的输出可以通过输出缓冲器（515）可编程地耦合到集成电路的I / O焊盘（520）。 逻辑模块可以绕过寄存器，并可直接通过输出缓冲器将其编程到I / O焊盘。 逻辑模块可以用作可共享的扩展器，通过可编程地将模块耦合到与耦合到全局互连的LAB中的其他逻辑模块的全局互连。

公开(公告)号：US06271681B1

公开(公告)日：2001-08-07

申请号：US09395886

申请日：1999-09-14

申请人： Richard G. Cliff ,  Francis B. Heile ,  Joseph Huang ,  David W. Mendel ,  Bruce B. Pedersen ,  Chiakang Sung ,  Kerry Veenstra ,  Bonnie I. Wang

发明人： Richard G. Cliff ,  Francis B. Heile ,  Joseph Huang ,  David W. Mendel ,  Bruce B. Pedersen ,  Chiakang Sung ,  Kerry Veenstra ,  Bonnie I. Wang

IPC分类号： H03K19177

CPC分类号： H03K19/1774 ,  H03K19/17744

摘要： A programmable logic integrated circuit device has several features which help it perform according to the PCI Special Interest Group's Peripheral Component Interface (“PCI”) signaling protocol. Regions of programmable logic within the device are closely coupled to the data signal output pins and clock signal input pins such that delay between application of a clock signal to the device and output of a data signal from the device is within PCI signal standards for delay. The device also includes output circuitry that can be configured to selectively invert signals to output enable and data input enable terminals of the output circuitry.

摘要翻译： 可编程逻辑集成电路器件具有几个功能，可帮助其根据PCI特殊兴趣组的外设组件接口（“PCI”）信令协议执行。 器件内的可编程逻辑区域紧密耦合到数据信号输出引脚和时钟信号输入引脚，使得施加时钟信号与器件之间的延迟和来自器件的数据信号的输出之间的延迟处于用于延迟的PCI信号标准之内。 该器件还包括可被配置为选择性地将信号反转到输出电路的输出使能和数据输入使能端的输出电路。

公开(公告)号：US06271680B1

公开(公告)日：2001-08-07

申请号：US09606250

申请日：2000-06-28

申请人： David W. Mendel ,  Richard G. Cliff

发明人： David W. Mendel ,  Richard G. Cliff

IPC分类号： H03K19177

CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17728

摘要： A logic element (300) for a programmable logic device. The logic element (300) allows two independent logic functions to be carried out during the same clock cycle. A 4-input look-up table (406) is provided using a 3-input look-up table (434) and two 2-input look-up tables. The results of the 4-input lookup table (406) and the 3-input lookup table (434) may be routed simultaneously from the logic element. It also allows a signal to be routed through a logic element (300) while carrying out an independent logic function. Carry logic (425) is provided. The results of the carry logic (486) may be routed to the global and local interconnect structure of the programmable logic device.

摘要翻译： 一种用于可编程逻辑器件的逻辑元件（300）。 逻辑元件（300）允许在相同的时钟周期内执行两个独立的逻辑功能。 使用3输入查找表（434）和两个2输入查找表来提供4输入查找表（406）。 可以从逻辑元件同时路由4输入查找表（406）和3输入查找表（434）的结果。 它还允许在执行独立的逻辑功能的同时通过逻辑元件（300）路由信号。 提供进位逻辑（425）。 进位逻辑（486）的结果可以被路由到可编程逻辑器件的全局和局部互连结构。

公开(公告)号：US06246260B1

公开(公告)日：2001-06-12

申请号：US09371440

申请日：1999-08-10

申请人： David W. Mendel

发明人： David W. Mendel

IPC分类号： H03K19177

CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17728

摘要： A logic element for a programmable logic device to implement a global shareable expander. The logic element includes logic modules (P0-P4) for implementing combinatorial logic and a register (445). The combinatorial and registered paths of a logic element may be utilized at the same time. The logic modules may be programmably coupled to the register. The output of the register may be programmably coupled through an output buffer (515) to an I/O pad (520) of the integrated circuit. The logic modules may bypass the register and directly programmably couple through the output buffer to the I/O pad. A logic module may be used as a shareable expander by programmably coupling the module through to a global interconnect with other logic modules in LABs coupled to the global interconnect.

摘要翻译： 可编程逻辑器件的逻辑元件，用于实现全局共享扩展器。 逻辑元件包括用于实现组合逻辑的逻辑模块（P0-P4）和寄存器（445）。 逻辑元件的组合和注册路径可以同时使用。 逻辑模块可以可编程地耦合到寄存器。 寄存器的输出可以通过输出缓冲器（515）可编程地耦合到集成电路的I / O焊盘（520）。 逻辑模块可以绕过寄存器，并可直接通过输出缓冲器将其编程到I / O焊盘。 逻辑模块可以用作可共享的扩展器，通过可编程地将模块耦合到与耦合到全局互连的LAB中的其他逻辑模块的全局互连。

公开(公告)号：US06204688B1

公开(公告)日：2001-03-20

申请号：US09208124

申请日：1998-12-09

申请人： Richard G. Cliff ,  Francis B. Heile ,  Joseph Huang ,  David W. Mendel ,  Bruce B. Pedersen ,  Chiakang Sung ,  Kerry Veenstra ,  Bonnie I. Wang

发明人： Richard G. Cliff ,  Francis B. Heile ,  Joseph Huang ,  David W. Mendel ,  Bruce B. Pedersen ,  Chiakang Sung ,  Kerry Veenstra ,  Bonnie I. Wang

IPC分类号： H03K19177

CPC分类号： H03K19/17736 ,  H03K19/04 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17796

摘要： A programmable logic array integrated circuit device includes a plurality of regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of such regions. Each row has a plurality of adjacent horizontal conductors, and each column has a plurality of adjacent vertical conductors. The regions in a row are interspersed with groups of local conductors which interconnect the adjacent regions and the associated horizontal and vertical conductors. The local conductors can also be used for intra-region communication, as well as communication between adjacent regions. Secondary signals such as clocks and clears for the regions can be drawn either from dedicated secondary signal conductors or normal region inputs. Memory cell requirements for region input signal selection are reduced by various techniques for sharing these memory cells.

摘要翻译： 可编程逻辑阵列集成电路器件包括以这种区域的交叉行和列的二维阵列布置在器件上的可编程逻辑的多个区域。 每行具有多个相邻的水平导体，并且每列具有多个相邻的垂直导体。 一排中的区域散布有互连相邻区域和相关联的水平和垂直导体的局部导体组。 本地导体也可用于区域内通信，以及相邻区域之间的通信。 辅助信号，例如时钟和区域的清除可以从专用辅助信号导体或正常区域输入中提取。 区域输入信号选择的存储单元要求通过用于共享这些存储单元的各种技术而减少。

公开(公告)号：US06184710B2

公开(公告)日：2001-02-06

申请号：US08924768

申请日：1997-08-27

申请人： David W. Mendel

发明人： David W. Mendel

IPC分类号： H03K19177

CPC分类号： H03K19/17736 ,  H03K19/17728

摘要： A programmable logic device has plural regions of programmable logic and a general-purpose interconnection network for conveying signals to, from, and between the regions. In addition to the general-purpose interconnection network, more direct interconnections are provided from outputs of each region to inputs of one or more other adjacent or nearby regions. At least some of these direct interconnections are preferably multiplexed with more conventional inputs to the other regions so that the input resources required for each region do not become excessive. The invention is particularly useful for devices which perform basic logic using sum-of-products (“Pterm”) logic. However, the invention is also useful in other types of devices such as those which perform basic logic using look-up tables.

摘要翻译： 可编程逻辑器件具有可编程逻辑的多个区域和用于向各区域之间和之间输送信号的通用互连网络。 除了通用互连网络之外，从每个区域的输出到一个或多个其他相邻或附近区域的输入提供更直接的互连。 这些直接互连中的至少一些优选地与更常规的输入复用到其他区域，使得每个区域所需的输入资源不会变得过大。 本发明对于使用产品总和（“Pterm”）逻辑执行基本逻辑的装置特别有用。 然而，本发明在诸如使用查找表执行基本逻辑的那些装置中也是有用的。

公开(公告)号：US6107822A

公开(公告)日：2000-08-22

申请号：US102828

申请日：1998-06-23

申请人： David W. Mendel ,  Richard G. Cliff

发明人： David W. Mendel ,  Richard G. Cliff

IPC分类号： H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17728

摘要： A logic element (300) for a programmable logic device. The logic element (300) allows two independent logic functions to be carried out during the same clock cycle. A 4-input look-up table (406) is provided using a 3-input look-up table (434) and two 2-input look-up tables. The results of the 4-input lookup table (406) and the 3-input lookup table (434) may be routed simultaneously from the logic element. It also allows a signal to be routed through a logic element (300) while carrying out an independent logic function. Carry logic (425) is provided. The results of the carry logic (486) may be routed to the global and local interconnect structure of the programmable logic device.

摘要翻译： 一种用于可编程逻辑器件的逻辑元件（300）。 逻辑元件（300）允许在相同的时钟周期内执行两个独立的逻辑功能。 使用3输入查找表（434）和两个2输入查找表来提供4输入查找表（406）。 可以从逻辑元件同时路由4输入查找表（406）和3输入查找表（434）的结果。 它还允许在执行独立的逻辑功能的同时通过逻辑元件（300）路由信号。 提供进位逻辑（425）。 进位逻辑（486）的结果可以被路由到可编程逻辑器件的全局和局部互连结构。

公开(公告)号：US5986465A

公开(公告)日：1999-11-16

申请号：US835557

申请日：1997-04-08

申请人： David W. Mendel

发明人： David W. Mendel

IPC分类号： H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17728

摘要： A logic element for a programmable logic device to implement a global shareable expander. The logic element includes logic modules (P0-P4) for implementing combinatorial logic and a register (445). The combinatorial and registered paths of a logic element may be utilized at the same time. The logic modules may be programmably coupled to the register. The output of the register may be programmably coupled through an output buffer (515) to an I/O pad (520) of the integrated circuit. The logic modules may bypass the register and directly programmably couple through the output buffer to the I/O pad. A logic module may be used as a shareable expander by programmably coupling the module through to a global interconnect with other logic modules in LABs coupled to the global interconnect.

摘要翻译： 可编程逻辑器件的逻辑元件，用于实现全局共享扩展器。 逻辑元件包括用于实现组合逻辑的逻辑模块（P0-P4）和寄存器（445）。 逻辑元件的组合和注册路径可以同时使用。 逻辑模块可以可编程地耦合到寄存器。 寄存器的输出可以通过输出缓冲器（515）可编程地耦合到集成电路的I / O焊盘（520）。 逻辑模块可以绕过寄存器，并可直接通过输出缓冲器将其编程到I / O焊盘。 逻辑模块可以用作可共享的扩展器，通过可编程地将模块耦合到与耦合到全局互连的LAB中的其他逻辑模块的全局互连。

公开(公告)号：US5341308A

公开(公告)日：1994-08-23

申请号：US702001

申请日：1991-05-17

申请人： David W. Mendel

发明人： David W. Mendel

IPC分类号： G06F17/50 ,  G06F15/60

CPC分类号： G06F17/5072

摘要： Circuit partitioning methods are enhanced by more accurately accounting for circuit nets which include connections external to the circuit being partitioned. The user can also prohibit movement of any circuit element or cell which the user does not want to have moved. The user can also prevent splitting of any net or set of cells which the user does not want to have split. The balance requirement of prior art methods is modified to allow circuit element moves which imbalance the partition. However, balance is ultimately restored by further circuit element moves.

摘要翻译： 通过更精确地计算包括被分割的电路外部的连接的电路网来增强电路划分方法。 用户还可以禁止用户不想移动的任何电路元件或单元的移动。 用户还可以防止用户不想拆分的任何网络或单元格的分割。 对现有技术方法的平衡要求进行了修改，以允许不均衡隔板的电路元件移动。 然而，通过进一步的电路元件移动最终还原平衡。