公开(公告)号：US20180095774A1

公开(公告)日：2018-04-05

申请号：US15282282

申请日：2016-09-30

Applicant: Amazon Technologies, Inc.

Inventor： Islam Mohamed Hatem Abdulfattah Mohamed Atta ,  Mark Bradley Davis ,  Robert Michael Johnson ,  Christopher Joseph Pettey ,  Asif Khan ,  Nafea Bshara

IPC: G06F9/455

Abstract: In a multi-tenant environment, separate virtual machines can be used for configuring and operating different subsets of programmable integrated circuits, such as a Field Programmable Gate Array (FPGA). The programmable integrated circuits can communicate directly with each other within a subset, but cannot communicate between subsets. Generally, all of the subsets of programmable ICs are within a same host server computer within the multi-tenant environment, and are sandboxed or otherwise isolated from each other so that multiple customers can share the resources of the host server computer without knowledge or interference with other customers.

公开(公告)号：US20180095670A1

公开(公告)日：2018-04-05

申请号：US15282148

申请日：2016-09-30

Applicant: Amazon Technologies, Inc.

Inventor： Mark Bradley Davis ,  Erez Izenberg ,  Robert Michael Johnson ,  Asif Khan ,  Islam Mohamed Hatem Abdulfattah Mohamed Atta ,  Nafea Bshara ,  Christopher Joseph Pettey

IPC: G06F3/06 ,  G06F13/28 ,  G11C7/10

CPC classification number: G06F3/0607 ,  G06F3/0635 ,  G06F3/0644 ,  G06F3/0685 ,  G06F13/28 ,  G06F15/7871 ,  G06F21/51 ,  G06F2221/2143 ,  G11C7/1072

Abstract: Methods and apparatus are disclosed for securely erasing partitions of reconfigurable logic devices such as FPGAs in a multi-tenant server environment. In one example, a method of securely erasing an FPGA includes identifying one partition of previously-programmed resources in the FPGA, erasing the identified partition by storing new values in memory or storage elements of the identified partition, and storing new values in memory or storage elements of additional external resources electrically connected to the integrated circuit and associated with the identified partition. Thus, other partitions and subsequent users of the identified partition are prevented from accessing the securely erased data. A configuration circuit, accessible by a host computer via DMA, can be programmed into the FPGA reconfigurable logic for performing the disclosed erasing operations.

公开(公告)号：US11474966B2

公开(公告)日：2022-10-18

申请号：US17184507

申请日：2021-02-24

Applicant: Amazon Technologies, Inc.

Inventor： Islam Atta ,  Christopher Joseph Pettey ,  Asif Khan ,  Robert Michael Johnson ,  Mark Bradley Davis ,  Erez Izenberg ,  Nafea Bshara ,  Kypros Constantinides

IPC: G06F13/40 ,  G06F9/445 ,  G06F13/42 ,  G06F15/78

Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a reconfigurable logic region. The reconfigurable logic region can include logic blocks that are configurable to implement application logic. The host logic can be used for encapsulating the reconfigurable logic region. The host logic can include a host interface for communicating with a processor. The host logic can include a management function accessible via the host interface. The management function can be adapted to cause the reconfigurable logic region to be configured with the application logic in response to an authorized request from the host interface. The host logic can include a data path function accessible via the host interface. The data path function can include a layer for formatting data transfers between the host interface and the application logic.

公开(公告)号：US11275503B2

公开(公告)日：2022-03-15

申请号：US16863700

申请日：2020-04-30

Applicant: Amazon Technologies, Inc.

Inventor： Mark Bradley Davis ,  Erez Izenberg ,  Robert Michael Johnson ,  Asif Khan ,  Islam Mohamed Hatem Abdulfattah Mohamed Atta ,  Nafea Bshara ,  Christopher Joseph Pettey

IPC: G06F3/06 ,  G06F12/08 ,  G06F15/78 ,  G06F21/51 ,  G06F13/28 ,  G11C7/10

Abstract: Methods and apparatus are disclosed for securely erasing partitions of reconfigurable logic devices such as FPGAs in a multi-tenant server environment. In one example, a method of securely erasing an FPGA includes identifying one partition of previously-programmed resources in the FPGA, erasing the identified partition by storing new values in memory or storage elements of the identified partition, and storing new values in memory or storage elements of additional external resources electrically connected to the integrated circuit and associated with the identified partition. Thus, other partitions and subsequent users of the identified partition are prevented from accessing the securely erased data. A configuration circuit, accessible by a host computer via DMA, can be programmed into the FPGA reconfigurable logic for performing the disclosed erasing operations.

公开(公告)号：US20220060454A1

公开(公告)日：2022-02-24

申请号：US17518259

申请日：2021-11-03

Applicant: Amazon Technologies, Inc.

Inventor： Islam Mohamed Hatem Abdulfattah Mohamed Atta ,  Christopher Joseph Pettey ,  Nafea Bshara ,  Asif Khan ,  Mark Bradley Davis ,  Prateek Tandon

IPC: H04L29/06 ,  H04L9/32 ,  G06F15/78 ,  G06F9/50

Abstract: The following description is directed to a logic repository service. In one example, a method of a logic repository service can include receiving a first request to generate configuration data for configurable hardware using a specification for application logic of the configurable hardware. The method can include generating the configuration data for the configurable hardware. The configuration data can include data for implementing the application logic. The method can include encrypting the configuration data to generate encrypted configuration data. The method can include signing the encrypted configuration data using a private key. The method can include transmitting the signed encrypted configuration data in response to the request.

公开(公告)号：US11182666B1

公开(公告)日：2021-11-23

申请号：US15805956

申请日：2017-11-07

Applicant: Amazon Technologies, Inc.

Inventor： Taylor Phebus ,  Asif Khan

IPC: G06N3/063 ,  H03K19/17728 ,  G06N3/04

Abstract: In one example, an integrated circuit includes a first circuit, a second circuit, a third circuit, and a fourth circuit. The first circuit is configured to receive an input value and generate a first intermediate value based on a first probability density distribution associated with the input value. The second circuit comprises a set of multiplexer circuits configured to select, from a first set of candidate values and based on the first intermediate value, a first product of the first intermediate value and a weight value. The third circuit is configured to generate a second intermediate value based on a sum of the first product and a second product received from another circuit. The fourth circuit is configured to generate an output value based on the second intermediate value and a second probability density distribution associated with the second intermediate value.

公开(公告)号：US10860357B1

公开(公告)日：2020-12-08

申请号：US15645624

申请日：2017-07-10

Applicant: Amazon Technologies, Inc.

Inventor： Robert Michael Johnson ,  Asif Khan ,  Nafea Bshara ,  Kiran Kalkunte Seshadri

IPC: G06F9/455 ,  G06F13/40 ,  G06F13/42

Abstract: A multi-tenant environment is described with a configurable hardware logic platform (e.g., a Field Programmable Gate Array (FPGA)) positioned on a host server computer. The configurable hardware logic platform can be programmed with a host logic wrapper portion, which is controlled by a service provider, and a customer portion, which is programmed with logic provided by a tenant of the service provider. While the host logic wrapper portion is reprogrammed, protections are put in place to prevent a virtual machine or the customer logic from violating security built within the host logic wrapper portion. Such protections can be suspending communications between the virtual machine and the customer logic until the host logic wrapper is reprogrammed.

公开(公告)号：US20200374191A1

公开(公告)日：2020-11-26

申请号：US16990765

申请日：2020-08-11

Applicant: Amazon Technologies, Inc.

Inventor： Asif Khan ,  Islam Mohamed Hatem Abdulfattah Mohamed Atta ,  Christopher Joseph Pettey ,  Kiran Kalkunte Seshadri ,  Nafea Bshara

IPC: H04L12/24 ,  G06F13/28 ,  H04L29/08 ,  H04L12/46 ,  G06F15/78 ,  G06F30/34 ,  G06F30/327 ,  G06F30/392 ,  G06F30/394 ,  G06F30/3323

Abstract: The following description is directed to a logic repository service supporting adaptable host logic. In one example, a method of a logic repository service can include receiving a first request to generate configuration data for configurable hardware using a specification for application logic. The method can include selecting a particular host logic shell from a group of host logic shells. The particular host logic shell can be used to encapsulate the application logic when the configurable hardware is configured. Configuration data for the configurable hardware can be generated. The configuration data can include data for implementing the application logic and at least a portion of the particular host logic shell. The method can include receiving a second request to download the configuration data to a host server computer comprising the configurable hardware. The configuration data can be transmitted to the host server computer in response to the second request.

公开(公告)号：US20200334186A1

公开(公告)日：2020-10-22

申请号：US16918151

申请日：2020-07-01

Applicant: Amazon Technologies, Inc.

Inventor： Asif Khan ,  Islam Mohamed Hatem Abdulfattah Mohamed Atta ,  Robert Michael Johnson ,  Mark Bradley Davis ,  Christopher Joseph Pettey ,  Nafea Bshara ,  Erez Izenberg

IPC: G06F13/362 ,  G06F13/40 ,  G06F9/50

Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a plurality of reconfigurable logic regions. Each reconfigurable region can include hardware that is configurable to implement an application logic design. The host logic can be used for separately encapsulating each of the reconfigurable logic regions. The host logic can include a plurality of data path functions where each data path function can include a layer for formatting data transfers between a host interface and the application logic of a corresponding reconfigurable logic region. The host interface can be configured to apportion bandwidth of the data transfers generated by the application logic of the respective reconfigurable logic regions.

公开(公告)号：US10795742B1

公开(公告)日：2020-10-06

申请号：US15638080

申请日：2017-06-29

Applicant: Amazon Technologies, Inc.

Inventor： Asif Khan ,  Sundeep Amirineni ,  Kiran Kalkunte Seshadri ,  Nafea Bshara

IPC: G06F11/07 ,  H04L12/24 ,  H04L12/26 ,  G06F16/635 ,  G06F11/30 ,  G06F15/16

Abstract: Disclosed are techniques regarding aspects of implementing client configurable logic within a computer system. The computer system can be a cloud infrastructure. The techniques can include determining that the client configurable logic has performed an errant action.