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    Method of measuring the impact of clock skew on slack during a statistical static timing analysis
    41.
    发明授权
    Method of measuring the impact of clock skew on slack during a statistical static timing analysis 有权
    在统计静态时序分析期间测量时钟偏移对松弛影响的方法

    公开(公告)号：US08578310B2

    公开(公告)日：2013-11-05

    申请号：US12857591

    申请日：2010-08-17

    申请人： Kerim Kalafala ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Vladimir Zolotov

    发明人： Kerim Kalafala ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Vladimir Zolotov

    IPC分类号： G06F9/455 ,  G06F17/50

    CPC分类号： G06F17/5031 ,  G06F2217/84

    摘要： Computing accurately and effectively the impact of clock skew on statistical slack in the presence of statistically variable timing quantities that accounts for both common path credit in the common portion of the clock tree, and RSS credit in the non-common of the clock tree. The clock skew is measured on a per launch and capture path-pair basis as a function of on the post-CPPR path-specific slack (including RSS credit), total mean value of latch-to-latch delay, RSS value of random latch-to-latch delay, test guard time and test adjust. The method includes: performing an initial block-based SSTA including CPPR analysis; selecting at least one launch and capture path-pair for skew analysis; for the at least one path pair, recording post CPPR slack, total mean value of latch-to-latch delay, RSS value of latch to latch delay, test guard time and test adjust; and quantifying the impact of clock skew on statistical slack thereof.

    摘要翻译： 计算时钟偏差对统计松弛的影响，存在统计上可变的时序量，这些时间量占时钟树共同部分的公共路径信誉，以及时钟树非共同的RSS信用。 时钟偏移在每个发射和捕获路径对的基础上测量，作为后CPPR路径特定松弛（包括RSS信用），锁存到锁存延迟的总平均值，随机锁存的RSS值的函数 到锁定延迟，测试保护时间和测试调整。 该方法包括：执行初始的基于块的SSTA，包括CPPR分析; 选择至少一个启动和捕获路径对进行​​偏差分析; 对于至少一个路径对，记录后CPPR松弛，锁存到锁存延迟的总平均值，锁存器的RSS值到锁存延迟，测试保护时间和测试调整; 并量化时钟偏移对其统计松弛的影响。

    SYSTEM AND METHOD FOR EFFICIENT MODELING OF NPSKEW EFFECTS ON STATIC TIMING TESTS
    44.
    发明申请
    SYSTEM AND METHOD FOR EFFICIENT MODELING OF NPSKEW EFFECTS ON STATIC TIMING TESTS 有权
    用于有效建模静态时间测试的NPSKEW效应的系统和方法

    公开(公告)号：US20120084066A1

    公开(公告)日：2012-04-05

    申请号：US12894286

    申请日：2010-09-30

    申请人： Nathan C. Buck ,  Brian M. Dreibelbis ,  John P. Dubuque ,  Eric A. Foreman ,  Peter A. Habitz ,  Jeffrey G. Hemmett ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Xiaoyue X. Wang

    发明人： Nathan C. Buck ,  Brian M. Dreibelbis ,  John P. Dubuque ,  Eric A. Foreman ,  Peter A. Habitz ,  Jeffrey G. Hemmett ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Xiaoyue X. Wang

    IPC分类号： G06F17/50

    CPC分类号： G06F13/105 ,  G06F11/261 ,  G06F17/50 ,  G06F17/5036

    摘要： A computer-implemented method that simulates NPskew effects on a combination NFET (Negative Field Effect Transistor)/PFET (Positive Field Effect Transistor) semiconductor device using slew perturbations includes performing a timing test by a computing device, by: (1) evaluating perturb slews in Strong N/Weak P directions on the combination semiconductor device for a timing test result; (2) evaluation perturb slews in Weak N/Strong P directions on the combination semiconductor device for a timing test result; and (3) evaluating unperturbed slews in a balanced condition on the combination semiconductor device for a timing test result. After each test is performed, a determination is made as to which evaluation of the perturbed and unperturbed slews produces a most conservative timing test result for the combination semiconductor device. An NPskew effect adjusted timing test result is finally output based on determining the most conservative timing test result.

    摘要翻译： 使用摆动扰动模拟组合NFET（负场效应晶体管）/ PFET（正场效应晶体管）/ PFET（正场效应晶体管））半导体器件的NPskew效应的计算机实现的方法包括通过以下方式执行计算设备的定时测试：（1）评估干扰压摆 在组合半导体器件上以强N /弱P方向进行定时测试结果; （2）组合半导体器件的评估扰动在弱N /强P方向上的时序测试结果; 和（3）在组合半导体器件上对平衡状态下的非扰动压摆进行定时测试结果。 在执行每个测试之后，确定扰动和未扰动的压摆的哪个评估对组合半导体器件产生最保守的定时测试结果。 基于确定最保守的定时测试结果，最终输出NPskew效果调整的定时测试结果。

    Method and device for selectively adding timing margin in an integrated circuit
    46.
    发明授权
    Method and device for selectively adding timing margin in an integrated circuit 有权
    用于在集成电路中选择性地添加定时裕度的方法和装置

    公开(公告)号：US08122409B2

    公开(公告)日：2012-02-21

    申请号：US11869306

    申请日：2007-10-09

    申请人： David E. Lackey ,  Chandramouli Visweswariah ,  Paul S. Zuchowski

    发明人： David E. Lackey ,  Chandramouli Visweswariah ,  Paul S. Zuchowski

    IPC分类号： G06F9/455 ,  G06F17/50

    CPC分类号： G06F17/5031 ,  G01R31/318307 ,  G01R31/318364

    摘要： A method, system, and integrated circuit including selectively added timing margin. The method, for integrating statistical timing and automatic test pattern generation (ATPG) to selectively add timing margin in an integrated circuit, includes identifying, while a chip is in design, paths that are unable to be robustly tested “at speed” during manufacturing test, running statistical timing to calculate a margin to be applied to the paths, updating design specifications for margin to be applied to the paths, and optimizing chip logic based on updated design specifications.

    摘要翻译： 一种方法，系统和集成电路，包括选择性地添加定时裕度。 用于集成统计时序和自动测试模式生成（ATPG）以在集成电路中选择性地添加时序裕度的方法包括在芯片设计时识别在制造测试期间“以速度”无法被鲁棒测试的路径 ，运行统计计时，计算要应用于路径的余量，更新要应用于路径的余量的设计规范，以及基于更新的设计规范优化芯片逻辑。

    Affinity-based clustering of vectors for partitioning the columns of a matrix
    47.
    发明授权
    Affinity-based clustering of vectors for partitioning the columns of a matrix 有权
    用于分割矩阵列的矢量的基于亲和度聚类

    公开(公告)号：US08112735B2

    公开(公告)日：2012-02-07

    申请号：US12020879

    申请日：2008-01-28

    申请人： Kerim Kalafala ,  Vasant Rao ,  Chandramouli Visweswariah

    发明人： Kerim Kalafala ,  Vasant Rao ,  Chandramouli Visweswariah

    IPC分类号： G06F17/50 ,  G06F13/00

    CPC分类号： G06F17/5031 ,  G06K9/6226 ,  G06K9/6247

    摘要： A computer system for partitioning the columns of a matrix A. The computer system includes a processor and a memory unit coupled to the processor. Program code in the memory unit, when executed by the processor, implements the method. Matrix A is provided in a memory device and has n columns and m rows; wherein n is an integer of at least 3; and wherein m is an integer of at least 1. The n columns is partitioned into a closed group of p clusters, p being a positive integer of at least 2 and less than n. The partitioning includes an affinity -based merging of clusters of pairs of clusters of the matrix A based on an affinity between the clusters in each pair of clusters being merged. Each cluster consists of one or more columns of matrix A. The p clusters are stored in a computer-readable storage device.

    摘要翻译： 一种用于分割矩阵A的列的计算机系统。计算机系统包括处理器和耦合到处理器的存储器单元。 当处理器执行时，存储器单元中的程序代码实现该方法。 矩阵A在存储器件中提供并具有n列和m行; 其中n为至少3的整数; 并且其中m是至少为1的整数。所述n列被划分成闭合的p个簇，p是至少为2且小于n的正整数。 分割包括基于在被合并的每对群集中的群集之间的亲和度的矩阵A的聚类对的基于亲和度的合并。 每个簇由矩阵A的一个或多个列组成.P个簇存储在计算机可读存储设备中。

    Methods for statistical slew propagation during block-based statistical static timing analysis
    48.
    发明授权
    Methods for statistical slew propagation during block-based statistical static timing analysis 有权
    基于块统计静态时序分析的统计转换传播方法

    公开(公告)号：US08086976B2

    公开(公告)日：2011-12-27

    申请号：US12121023

    申请日：2008-05-15

    申请人： Jeffrey G. Hemmett ,  Chandramouli Visweswariah ,  Vladimir Zolotov

    发明人： Jeffrey G. Hemmett ,  Chandramouli Visweswariah ,  Vladimir Zolotov

    IPC分类号： G06F9/455 ,  G06F17/50

    CPC分类号： G06F17/5031 ,  G06F2217/84

    摘要： Methods for statistical slew propagation in static statistical timing analysis. The method includes projecting a canonical approximation of an input slew over a timing path to a first corner and using the projected input slew to calculate a delay and an output slew at the first corner. The method further includes perturbing the canonical approximation of the input slew to a different corner, calculating a delay and an output slew at the different corner using the perturbed input slew canonical, and determining a sensitivity of the delay and the output slew to a plurality of parameters, simultaneous with implicit sensitivity calculations to the input slew, with finite difference calculations between the first corner and perturbed data.

    摘要翻译： 静态统计时序分析中统计转换传播的方法。 该方法包括将定时路径上的输入转换的规范近似投影到第一角，并且使用投影输入转换来计算在第一角处的延迟和输出。 该方法进一步包括将输入转换的规范近似扰乱到不同的角，使用干扰的输入转换来计算延迟和在不同角上的输出转换，并且将延迟和输出转换的灵敏度确定为多个 参数，同时与隐式灵敏度计算到输入转换，在第一个角和扰动数据之间进行有限差分计算。

    System and method for accommodating non-gaussian and non-linear sources of variation in statistical static timing analysis
    50.
    发明授权
    System and method for accommodating non-gaussian and non-linear sources of variation in statistical static timing analysis 有权
    用于在统计静态时序分析中调节非高斯和非线性变化源的系统和方法

    公开(公告)号：US08015525B2

    公开(公告)日：2011-09-06

    申请号：US12114203

    申请日：2008-05-02

    申请人： Hongliang Chang ,  Sambasivan Narayan ,  Chandramouli Visweswariah ,  Vladimir Zolotov

    发明人： Hongliang Chang ,  Sambasivan Narayan ,  Chandramouli Visweswariah ,  Vladimir Zolotov

    IPC分类号： G06F9/455 ,  G06F17/50

    CPC分类号： G06F17/5031

    摘要： There is provided a system and method for statistical timing analysis and optimization of an electrical circuit having two or more digital elements. The system includes at least one parameter input and a statistical static timing analyzer and electrical circuit optimizer. The at least one parameter input is for receiving parameters of the electrical circuit. At least one of the parameters has at least one of a non-Gaussian probability distribution and a non-linear delay effect. The statistical static timing analyzer and electrical circuit optimizer is for calculating at least one of a signal arrival time and a signal required time for the electrical circuit using the at least one parameter and for modifying a component size of the electrical circuit to alter gate timing characteristics of the electrical circuit based upon the at least one of the signal arrival time and the signal required time.

    摘要翻译： 提供了一种用于具有两个或多个数字元件的电路的统计时序分析和优化的系统和方法。 该系统包括至少一个参数输入和统计静态时序分析器和电路优化器。 至少一个参数输入用于接收电路的参数。 至少一个参数具有非高斯概率分布和非线性延迟效应中的至少一个。 统计静态时序分析器和电路优化器用于使用至少一个参数来计算电路的信号到达时间和信号所需时间中的至少一个，并且用于修改电路的组件尺寸以改变门时序特性 基于信号到达时间和信号所需时间中的至少一个。