公开(公告)号：US08560989B2

公开(公告)日：2013-10-15

申请号：US13311832

申请日：2011-12-06

申请人： Nathan Buck ,  Brian Dreibelbis ,  John P. Dubuque ,  Eric A. Foreman ,  James C. Gregerson ,  Peter A. Habitz ,  Jeffrey G. Hemmett ,  Debjit Sinha ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Michael H. Wood ,  Vladimir Zolotov

发明人： Nathan Buck ,  Brian Dreibelbis ,  John P. Dubuque ,  Eric A. Foreman ,  James C. Gregerson ,  Peter A. Habitz ,  Jeffrey G. Hemmett ,  Debjit Sinha ,  Natesan Venkateswaran ,  Chandramouli Visweswariah ,  Michael H. Wood ,  Vladimir Zolotov

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F2217/10 ,  G06F2217/62

摘要： Systems and methods for statistical clock cycle computation and closing timing of an integrated circuit design to a maximum clock cycle or period. The method includes loading a design and timing model for at least one circuit path of an integrated circuit or a region of the integrated circuit into a computing device. The method further includes performing a statistical static timing analysis (SSTA) of the at least one circuit path using the loaded design and timing model to obtain slack canonical data. The method further includes calculating a maximum circuit clock cycle for the integrated circuit or the specified region of the integrated circuit in linear canonical form based upon the slack canonical data obtained from the SSTA.

摘要翻译： 将集成电路设计的统计时钟周期计算和闭合时序的系统和方法设计到最大时钟周期或周期。 该方法包括将用于集成电路或集成电路的区域的至少一个电路路径的设计和定时模型加载到计算设备中。 该方法还包括使用加载的设计和定时模型来执行至少一个电路路径的统计静态时序分析（SSTA），以获得松散的规范数据。 该方法还包括基于从SSTA获得的松弛规范数据，以线性规范形式计算集成电路或集成电路的指定区域的最大电路时钟周期。

公开(公告)号：US20140040844A1

公开(公告)日：2014-02-06

申请号：US13564751

申请日：2012-08-02

申请人： Chandramouli Visweswariah ,  Eric Fluhr ,  Stephen G. Shuma ,  Debjit Sinha ,  Michael H. Wood

发明人： Chandramouli Visweswariah ,  Eric Fluhr ,  Stephen G. Shuma ,  Debjit Sinha ,  Michael H. Wood

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： Method for performing timing closure of integrated circuits in the presence of manufacturing and environmental variations. The starting design is analyzed using statistical static timing analysis to determine timing violations. Each timing violation in its statistical canonical form is examined. In a first aspect of the invention, the canonical failing slack is inspected to determine what type of move is most likely to fix the timing violation taking into account all relevant manufacturing and environmental variations. In a second aspect of the invention, pre-characterized moves such as insertion of delay pad cells are evaluated for their ability to fix the timing violation without triggering timing, and the best move or set of moves is selected.

摘要翻译： 在存在制造和环境变化的情况下执行集成电路的定时关闭的方法。 使用统计静态时序分析来分析起始设计，以确定时序违规。 检查其统计规范形式的每个时间违规。 在本发明的第一方面，检查规范的故障松弛以确定哪种类型的移动最有可能在考虑到所有相关的制造和环境变化的情况下修复定时违规。 在本发明的第二方面中，评估了诸如插入延迟垫单元之类的预先表征的移动能够固定定时违反而不触发定时，并且选择最佳移动或移动集合。

公开(公告)号：US08732642B2

公开(公告)日：2014-05-20

申请号：US13564751

申请日：2012-08-02

申请人： Chandramouli Visweswariah ,  Eric Fluhr ,  Stephen G. Shuma ,  Debjit Sinha ,  Michael H. Wood

发明人： Chandramouli Visweswariah ,  Eric Fluhr ,  Stephen G. Shuma ,  Debjit Sinha ,  Michael H. Wood

IPC分类号： G06F9/455

CPC分类号： G06F17/5031

摘要： Method for performing timing closure of integrated circuits in the presence of manufacturing and environmental variations. The starting design is analyzed using statistical static timing analysis to determine timing violations. Each timing violation in its statistical canonical form is examined. In a first aspect of the invention, the canonical failing slack is inspected to determine what type of move is most likely to fix the timing violation taking into account all relevant manufacturing and environmental variations. In a second aspect of the invention, pre-characterized moves such as insertion of delay pad cells are evaluated for their ability to fix the timing violation without triggering timing, and the best move or set of moves is selected.

摘要翻译： 在存在制造和环境变化的情况下执行集成电路的定时关闭的方法。 使用统计静态时序分析来分析起始设计，以确定时序违规。 检查其统计规范形式的每个时间违规。 在本发明的第一方面，检查规范的故障松弛以确定哪种类型的移动最有可能在考虑到所有相关的制造和环境变化的情况下修复定时违规。 在本发明的第二方面中，评估了诸如插入延迟垫单元之类的预先表征的移动能够固定定时违反而不触发定时，并且选择最佳移动或移动集合。

公开(公告)号：US06959930B2

公开(公告)日：2005-11-01

申请号：US10438474

申请日：2003-05-15

申请人： Michael H. Wood ,  Ernest B. McCurdy

发明人： Michael H. Wood ,  Ernest B. McCurdy

IPC分类号： F16J15/26 ,  F16J9/12

CPC分类号： F16J15/26

摘要： A ring assembly, including a first oil scraper ring, a center oil scraper ring and a gas seal ring, adapted for disposition in a single groove of a packing cup which can be stationarily mounted over and around a reciprocally movable piston rod of a gas compressor. The function of the assembly is to both scrape lubricating oil from the piston rod for return to one side of the cup and to provide a seal against gas leakage from an opposite side of the cup, both along the piston rod under the seal ring and between the seal ring and opposing sides of the center ring and groove to prevent mixing of gas with the oil and escape of gas from the compressor. The center ring features a tapered outer peripheral surface portion. An annular side loading element, which can be a garter spring, is mounted in compression around the center ring so as to bear against the tapered surface portion and against an adjacent side of the first ring. The element thus side loads the first ring, by urging it against one side of the groove and oppositely side loads the center ring and seal ring to force one against the other and to urge the seal ring tightly against an opposite side wall of the groove to effect a satisfactory gas seal. The first ring and center ring, together, provide three separate and axially spaced apart oil scraper edges.

摘要翻译： 一种环组件，包括第一刮油环，中心刮油环和气密封环，其适于配置在填料杯的单个槽中，其可以固定地安装在气体压缩机的往复运动的活塞杆上 。 该组件的功能是既要从活塞杆上刮去润滑油，以便返回到杯的一侧，并且提供密封件，以防止来自杯的相对侧的气体泄漏，两者沿密封圈下方的活塞杆和第二 密封环和中心环和槽的相对侧，以防止气体与油的混合和气体从压缩机逸出。 中心环具有锥形外周面部分。 环形侧装载元件可以是一个拉杆弹簧，围绕中心环压缩安装，以抵靠锥形表面部分并抵靠第一环的相邻侧。 因此，元件通过将其推向槽的一侧来加载第一环，并且相反侧装载中心环和密封环以迫使一个抵靠另一个并且将密封环紧紧地推靠在槽的相对侧壁上 实现令人满意的气密封。 第一环和中心环一起提供三个独立且轴向隔开的刮油边。

公开(公告)号：US5563517A

公开(公告)日：1996-10-08

申请号：US442556

申请日：1995-05-16

申请人： Glenn A. Biery ,  Daniel M. Boyne ,  Kenneth P. Rodbell ,  Richard G. Smith ,  Michael H. Wood

发明人： Glenn A. Biery ,  Daniel M. Boyne ,  Kenneth P. Rodbell ,  Richard G. Smith ,  Michael H. Wood

IPC分类号： G01R31/26 ,  G01R29/26 ,  H01L21/66

CPC分类号： G01R29/26

摘要： A test system having an improved physical layout and electrical design allows the 1/f noise of metal interconnects to be measured at levels close to that of Johnson or thermal noise. A detailed description of examples of operation of the test system provides evidence of the effectiveness of the test system in minimizing system noise to a level significantly lower than Johnson noise. This permits quantitative measurment of the noise contribution attributable to variations in cross-sectional area of connections for various applications and for qualitative prediction of electromigration lifetimes of metal films, particularly aluminum, having different microstructures. The test system includes an enclosure which includes several nested groups of housings including a sample oven within a device under test box which is, in turn, contained within the system enclosure. Wire wound resistors powered by a DC power supply are used to provide heating without interfering with measurement of 1/f noise of a device under test (D.U.T.). A biasing circuit and a bank of batteries are also provided with separate enclosures within the system enclosure.

摘要翻译： 具有改进的物理布局和电气设计的测试系统允许以接近Johnson或热噪声的水平测量金属互连的1 / f噪声。 测试系统操作示例的详细描述提供了测试系统在将系统噪声降至明显低于约翰逊噪声水平的有效性的证据。 这允许由于各种应用的连接的横截面积的变化以及用于定性预测具有不同微结构的金属膜，特别是铝的电迁移寿命的噪声贡献的定量测量。 该测试系统包括一个外壳，该外壳包括若干嵌套的外壳组，其中包括在被测箱的设备内的样品烘箱，该烘箱也被包含在系统外壳内。 由直流电源供电的绕线电阻器用于提供加热，而不会干扰被测器件（D.U.T.）的1 / f噪声的测量。 偏置电路和电池组还在系统外壳内设置有单独的外壳。

公开(公告)号：US07681169B2

公开(公告)日：2010-03-16

申请号：US11846577

申请日：2007-08-29

申请人： Christopher J. Berry ,  Michael A. Bowen ,  Michael R. Scheuermann ,  Michael H. Wood

发明人： Christopher J. Berry ,  Michael A. Bowen ,  Michael R. Scheuermann ,  Michael H. Wood

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： A method for pre-wiring through multiple levels of metal using flues includes steps of: receiving information comprising flue geometries and flue properties; producing multiple routing patterns of a design for the flues; identifying macro instance terminals to be pre-wired in the design; selecting at least one of the routing patterns for the macro instance terminals in the design to avoid blockage; and instantiating the design such that the flues can be manipulated as vias.

摘要翻译： 使用烟道预先接线多层金属的方法包括以下步骤：接收包括烟道几何形状和烟道特性的信息; 生成针对流感的设计的多个路由模式; 识别要在设计中预先布线的宏实例终端; 在设计中选择用于宏实例终端的路由模式中的至少一个以避免阻塞; 并实例化设计，使得烟道可以被操纵为过孔。

公开(公告)号：US06758219B2

公开(公告)日：2004-07-06

申请号：US10237327

申请日：2002-09-06

申请人： James A. Sapala ,  Michael H. Wood

发明人： James A. Sapala ,  Michael H. Wood

IPC分类号： A61B1900

CPC分类号： A61F5/0083 ,  A61B17/1114 ,  A61B2017/1135 ,  A61F2/02

摘要： The present invention is an improved gastric bypass, a surgical method to treat clinically significant obesity, in which the likelihood of post-surgical complications is reduced.

摘要翻译： 本发明是改进的胃旁路手术，一种治疗临床上显着的肥胖症的手术方法，其中手术后并发症的可能性降低。

公开(公告)号：US5434385A

公开(公告)日：1995-07-18

申请号：US970370

申请日：1992-11-02

申请人： Glenn A. Biery ,  Daniel M. Boyne ,  Kenneth P. Rodbell ,  Richard G. Smith ,  Michael H. Wood

发明人： Glenn A. Biery ,  Daniel M. Boyne ,  Kenneth P. Rodbell ,  Richard G. Smith ,  Michael H. Wood

IPC分类号： G01R31/26 ,  G01R29/26 ,  H01L21/66 ,  F27D11/02 ,  H02H7/04 ,  H05B11/00

CPC分类号： G01R29/26

摘要： A test system having an improved physical layout and electrical design allows the 1/f noise of metal interconnects to be measured at levels close to that of Johnson or thermal noise. A detailed description of examples of operation of the test system provides evidence of the effectiveness of the test system in minimizing system noise to a level significantly lower than Johnson noise. This permits quantitative measurment of the noise contribution attributable to variations in cross-sectional area of connections for various applications and for qualitative prediction of electromigration lifetimes of metal films, particularly aluminum, having different microstructures. The test system includes an enclosure which includes several nested groups of housings including a sample oven within a device under test box which is, in turn, contained within the system enclosure. Wire wound resistors powered by a DC power supply are used to provide heating without interfering with measurement of 1/f noise of a device under test (D.U.T.). A biasing circuit and a bank of batteries are also provided with separate enclosures within the system enclosure.

摘要翻译： 具有改进的物理布局和电气设计的测试系统允许以接近Johnson或热噪声的水平测量金属互连的1 / f噪声。 测试系统操作示例的详细描述提供了测试系统在将系统噪声降至明显低于约翰逊噪声水平的有效性的证据。 这允许由于各种应用的连接的横截面积的变化以及用于定性预测具有不同微结构的金属膜，特别是铝的电迁移寿命的噪声贡献的定量测量。 该测试系统包括一个外壳，该外壳包括若干嵌套的外壳组，其中包括在被测箱的设备内的样品烘箱，该烘箱也被包含在系统外壳内。 由直流电源供电的绕线电阻器用于提供加热，而不会干扰被测器件（D.U.T.）的1 / f噪声的测量。 偏置电路和电池组还在系统外壳内设置有单独的外壳。

公开(公告)号：US06658610B1

公开(公告)日：2003-12-02

申请号：US09669117

申请日：2000-09-25

申请人： Chiaming Chai ,  Jeffrey H. Fischer ,  Michael R. Ouellette ,  Michael H. Wood

发明人： Chiaming Chai ,  Jeffrey H. Fischer ,  Michael R. Ouellette ,  Michael H. Wood

IPC分类号： G11C2900

CPC分类号： G01R31/3187 ,  G01R31/3193 ,  G11C29/26 ,  G11C2029/1802

摘要： The present invention provides a method and apparatus that improves Built-In-Self-Test (BIST) flexibility without requiring the complexity of a compilable BIST circuit. Additionally, the present invention provides the ability to use a single BIST to test multiple memory arrays of different sizes. The preferred embodiment of the present invention provides a compilable address magnitude comparator to facilitate BIST testing of different size memory arrays without requiring customization of the BIST controller. The preferred embodiment compilable address magnitude comparator is compiled within the compilable memory arrays of the ASIC to allow a single BIST controller to test multiple sizes of memory arrays without requiring that the BIST controller itself be compilable. In the preferred embodiment, the compilable magnitude address comparator overrides the self-test signal from the BIST when the BIST attempts to test addresses that do not exist in the memory. As such, the BIST is prevented from writing to addresses that do not exist, and does not receive error signals from those addresses. Thus, the BIST controller is able to test memory arrays without regard for their particular size. Furthermore, a single BIST controller can then be used to test multiple memory arrays of different sizes in the ASIC, again reducing device complexity.

摘要翻译： 本发明提供了一种改进内置自测（BIST）灵活性的方法和装置，而不需要可编译BIST电路的复杂性。 此外，本发明提供了使用单个BIST来测试不同大小的多个存储器阵列的能力。 本发明的优选实施例提供可编译的地址幅度比较器，以便于不需要定制BIST控制器的不同大小的存储器阵列的BIST测试。 优选实施例可编译地址幅度比较器被编译在ASIC的可编译存储器阵列内，以允许单个BIST控制器测试存储器阵列的多个大小，而不需要BIST控制器本身可编译。 在优选实施例中，当BIST尝试测试存储器中不存在的地址时，可编译幅度地址比较器覆盖来自BIST的自检信号。 因此，BIST被阻止写入不存在的地址，并且不从这些地址接收到错误信号。 因此，BIST控制器能够测试存储器阵列，而不考虑其特定大小。 此外，可以使用单个BIST控制器来测试ASIC中不同大小的多个存储器阵列，从而降低器件的复杂性。

公开(公告)号：US08468306B2

公开(公告)日：2013-06-18

申请号：US12031858

申请日：2008-02-15

申请人： Aaron Tsai ,  Barry W. Krumm ,  James R. Mitchell ,  Bradley Nelson ,  Brian D. Barrick ,  Chung-Lung Kevin Shum ,  Michael H. Wood

发明人： Aaron Tsai ,  Barry W. Krumm ,  James R. Mitchell ,  Bradley Nelson ,  Brian D. Barrick ,  Chung-Lung Kevin Shum ,  Michael H. Wood

IPC分类号： G06F9/38

CPC分类号： G06F12/0804 ,  G06F9/30043

摘要： A pipelined processor includes circuitry adapted for store forwarding, including: for each store request, and while a write to one of a cache and a memory is pending; obtaining the most recent value for at least one block of data; merging store data from the store request with the block of data thus updating the block of data and forming a new most recent value and an updated complete block of data; and buffering the updated block of data into a store data queue; for each additional store request, where the additional store request requires at least one updated block of data: determining if store forwarding is appropriate for the additional store request on a block-by-block basis; if store forwarding is appropriate, selecting an appropriate block of data from the store data queue on a block-by-block basis; and forwarding the selected block of data to the additional store request.

摘要翻译： 流水线处理器包括适于商店转发的电路，包括：对于每个存储请求，以及在对高速缓存和存储器中的一个进行写入待处理的情况下; 获取至少一个数据块的最新值; 将来自存储请求的存储数据与数据块合并，从而更新数据块并形成新的最新值和更新的完整数据块; 以及将更新的数据块缓冲到存储数据队列中; 对于每个额外的存储请求，其中附加存储请求需要至少一个更新的数据块：确定存储转发是否适合逐块的附加存储请求; 如果存储转发是适当的，则在逐块的基础上从存储数据队列中选择适当的数据块; 以及将所选择的数据块转发到附加存储请求。