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82 条记录 (耗时 0.033 秒)

    Using a threshold value to control mid-interrupt polling
    43.
    发明申请
    Using a threshold value to control mid-interrupt polling 有权
    使用阈值来控制中间中断轮询

    公开(公告)号：US20050223133A1

    公开(公告)日：2005-10-06

    申请号：US10973790

    申请日：2004-10-25

    申请人： Sujoy Sen ,  Anil Vasudevan ,  Linden Cornett ,  Prafulla Deuskar

    发明人： Sujoy Sen ,  Anil Vasudevan ,  Linden Cornett ,  Prafulla Deuskar

    IPC分类号： G06F13/28 ,  G06F15/173 ,  H01L29/40 ,  H04L12/56 ,  H04L29/06

    CPC分类号： H04L49/9042 ,  H04L47/50 ,  H04L49/90 ,  H04L69/16 ,  H04L69/161 ,  H04L69/163

    摘要： In one embodiment, a method is provided. The method of this embodiment provides performing packet processing on a packet, and placing the packet in a placement queue; if no read buffer is available, determining if the size of the placement queue exceeds a threshold polling value; and if the size of the placement queue exceeds the threshold polling value: if there are one or more pending DMM (data movement module) requests, polling a DMM to determine if the DMM has completed the one or more pending DMM requests for data associated with an application; and if the DMM has completed the one or more pending DMM requests, then sending a completion notification to the application to receive the data.

    摘要翻译： 在一个实施例中，提供了一种方法。 本实施例的方法提供对分组执行分组处理，并将分组置于放置队列中; 如果没有读取缓冲区可用，则确定布局队列的大小是否超过阈值轮询值; 并且如果布置队列的大小超过阈值轮询值：如果存在一个或多个待处理的DMM（数据移动模块）请求，则轮询DMM以确定DMM是否已经完成了与一个或多个待处理DMM 一个应用程序; 并且如果DMM已经完成了一个或多个待处理的DMM请求，则向应用发送完成通知以接收数据。

    Accelerated TCP (Transport Control Protocol) stack processing
    44.
    发明申请
    Accelerated TCP (Transport Control Protocol) stack processing 有权
    加速TCP（传输控制协议）堆栈处理

    公开(公告)号：US20050223128A1

    公开(公告)日：2005-10-06

    申请号：US10815895

    申请日：2004-03-31

    申请人： Anil Vasudevan ,  Dennis Bell ,  David Minturn ,  Sujoy Sen

    发明人： Anil Vasudevan ,  Dennis Bell ,  David Minturn ,  Sujoy Sen

    IPC分类号： G06F13/28 ,  G06F15/173 ,  H01L29/40 ,  H04L12/56 ,  H04L29/06

    CPC分类号： H04L49/9042 ,  H04L47/50 ,  H04L49/90 ,  H04L69/16 ,  H04L69/161 ,  H04L69/163

    摘要： In one embodiment, a method is provided. The method of this embodiment provides receiving an indication on a network component that one or more packets have been received from a network; the network component notifying a TCP-A (transport control protocol—accelerated) driver that the one or more packets have arrived; a TCP-A driver performing packet processing for at least one of the one or more packets; and the TCP-A driver performing one or more operations that result in a data movement module placing one or more corresponding payloads of the at least one of the one or more packets into a read buffer.

    摘要翻译： 在一个实施例中，提供了一种方法。 该实施例的方法提供在网络组件上接收到从网络接收到一个或多个分组的指示; 所述网络组件通知所述一个或多个分组已经到达的TCP-A（传输控制协议加速）驱动程序; 对所述一个或多个分组中的至少一个分组执行分组处理的TCP-A驱动器; 执行一个或多个操作的TCP-A驱动程序，其导致数据移动模块将一个或多个分组中的至少一个分组的一个或多个对应的有效载荷放入读取缓冲器。

    Method and apparatus for improving the efficiency of interrupt delivery at runtime in a network system
    46.
    发明授权
    Method and apparatus for improving the efficiency of interrupt delivery at runtime in a network system 有权
    一种提高网络系统运行时中断传输效率的方法和装置

    公开(公告)号：US08296490B2

    公开(公告)日：2012-10-23

    申请号：US11771209

    申请日：2007-06-29

    申请人： Yadong Li ,  Sujoy Sen

    发明人： Yadong Li ,  Sujoy Sen

    IPC分类号： G06F13/24 ,  G06F15/16 ,  G06F3/00

    CPC分类号： G06F9/3861 ,  G06F13/24 ,  H04L49/90

    摘要： Processor affinity of an application/thread may be used to deliver an interrupt caused by the application/thread to a best processor at runtime. The processor to which the interrupt is delivered may either run the target application/thread or be located in the same socket as the processor that runs the target application/thread. The processor affinity of the application/thread may be pushed down at runtime to a network device, a chipset, a memory control hub (“MCH”), or an input/output hub (“IOH”), which will facilitate delivery of the interrupt using that affinity information.

    摘要翻译： 应用程序/线程的处理器亲和性可能用于在运行时将由应用程序/线程引起的中断传递到最佳处理器。 发送中断的处理器可以运行目标应用程序/线程，也可以位于与运行目标应用程序/线程的处理器相同的套接字中。 应用程序/线程的处理器亲和性可能在运行时被推下到网络设备，芯片组，存储器控制集线器（MCH）或输入/输出集线器（IOH），这将有助于使用该亲和力传送中断 信息。

    Packet coalescing
    48.
    发明申请
    Packet coalescing 有权

    公开(公告)号：US20060104303A1

    公开(公告)日：2006-05-18

    申请号：US10991239

    申请日：2004-11-16

    申请人： Srihari Makineni ,  Ravi Iyer ,  Dave Minturn ,  Sujoy Sen ,  Donald Newell ,  Li Zhao

    发明人： Srihari Makineni ,  Ravi Iyer ,  Dave Minturn ,  Sujoy Sen ,  Donald Newell ,  Li Zhao

    IPC分类号： H04L12/28

    CPC分类号： H04L45/74 ,  H04L49/20 ,  H04L69/16 ,  H04L69/161 ,  H04L69/166

    摘要： In general, in one aspect, the disclosures describes a method that includes receiving multiple ingress Internet Protocol packets, each of the multiple ingress Internet Protocol packets having an Internet Protocol header and a Transmission Control Protocol segment having a Transmission Control Protocol header and a Transmission Control Protocol payload, where the multiple packets belonging to a same Transmission Control Protocol/Internet Protocol flow. The method also includes preparing an Internet Protocol packet having a single Internet Protocol header and a single Transmission Control Protocol segment having a single Transmission Control Protocol header and a single payload formed by a combination of the Transmission Control Protocol segment payloads of the multiple Internet Protocol packets. The method further includes generating a signal that causes receive processing of the Internet Protocol packet.

    Distributing timers across processors
    49.
    发明申请
    Distributing timers across processors 失效
    在处理器之间分配计时器

    公开(公告)号：US20060031588A1

    公开(公告)日：2006-02-09

    申请号：US10882521

    申请日：2004-06-30

    申请人： Sujoy Sen ,  Linden Cornett ,  Prafulla Deuskar ,  David Minturn

    发明人： Sujoy Sen ,  Linden Cornett ,  Prafulla Deuskar ,  David Minturn

    IPC分类号： G06F15/16 ,  G06F1/12

    CPC分类号： H04L69/16 ,  H04L69/161 ,  H04L69/28

    摘要： In general, in one aspect, the disclosure describes a method of maintaining network protocol timers in data structures associated with different respective processors in a multi-processor system. The timers accessed by a respective one of the processors include timers of connections mapped to the processor.

    摘要翻译： 通常，在一个方面，本公开描述了在多处理器系统中维护与不同相应处理器相关联的数据结构中的网络协议定时器的方法。 由相应的一个处理器访问的定时器包括映射到处理器的连接的定时器。

    TECHNOLOGIES FOR REMOTE NETWORKED ACCELERATORS
    50.
    发明申请
    TECHNOLOGIES FOR REMOTE NETWORKED ACCELERATORS 审中-公开

    公开(公告)号：US20200073849A1

    公开(公告)日：2020-03-05

    申请号：US16402507

    申请日：2019-05-03

    申请人： Paul H. Dormitzer ,  Susanne M. Balle ,  Sujoy Sen ,  Evan Custodio

    发明人： Paul H. Dormitzer ,  Susanne M. Balle ,  Sujoy Sen ,  Evan Custodio

    IPC分类号： G06F15/173 ,  G06F13/42

    摘要： Technologies for network interface controllers (NICs) include a computing device having a NIC coupled to a root FPGA via an I/O link. The root FPGA is further coupled to multiple worker FPGAs by a serial link with each worker FPGA. The NIC may receive a remote direct memory access (RDMA) message from a remote host and send the RDMA message to the root FPGA via the I/O link. The root FPGA determines a target FPGA based on a memory address of the RDMA message. Each FPGA is associated with a part of a unified address space. If the target FPGA is a worker FPGA, the root FPGA sends the RDMA message to the worker FPGA via the corresponding serial link, and the worker FPGA processes the RDMA message. If the root FPGA is the target, the root FPGA may process the RDMA message. Other embodiments are described and claimed.