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41.发明申请公开(公告)号：US20140070217A1
公开(公告)日：2014-03-13
申请号：US13963372
申请日：2013-08-09
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Zheng LIU , Chunping LONG , Pil Seok KIM
IPC: H01L29/786 , H01L29/66
CPC classification number: H01L29/78669 , H01L29/66757 , H01L29/66765
Abstract: The disclosure discloses a thin film transistor and a manufacturing method thereof, an array substrate, and a display device, which can manufacture a thin film transistor with lower contents of impurity at a low temperature. The thin film transistor comprises: a substrate, and an active layer disposed on the substrate, the active layer comprising a source region, a drain region and a channel region, wherein the active layer is formed by depositing an inducing metal on an amorphous silicon layer on the substrate by an atomic layer deposition (ALD) method and then conducting heat treatment on the amorphous silicon layer deposited with the inducing metal so that metal induction crystallization and metal induction lateral crystallization take place in the amorphous silicon layer.
Abstract translation: 本发明公开了一种薄膜晶体管及其制造方法，阵列基板和显示装置，其可以在低温下制造具有较低杂质含量的薄膜晶体管。 所述薄膜晶体管包括：衬底和设置在所述衬底上的有源层，所述有源层包括源极区，漏极区和沟道区，其中所述有源层通过在非晶硅层上沉积诱导金属而形成 通过原子层沉积（ALD）方法在衬底上，然后对沉积有诱导金属的非晶硅层进行热处理，使得金属诱导结晶和金属诱导横向结晶发生在非晶硅层中。
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公开(公告)号：US20240241415A1
公开(公告)日：2024-07-18
申请号：US18574261
申请日：2023-01-10
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Lizhong WANG , Guangcai YUAN , Ce NING , Jianbo XIAN , Liping LEI , Chunping LONG , Yunping DI , Binbin TONG , Zhen ZHANG
IPC: G02F1/1368 , G02F1/1362
CPC classification number: G02F1/1368 , G02F1/136222 , G02F1/136286
Abstract: An array substrate and a display panel. The array substrate includes: a base substrate; a gate line and a data line on the base substrate, the gate line intersect the data line to define a pixel region; a metal oxide thin film transistor is arranged in the pixel region, the metal oxide thin film transistor includes a metal oxide semiconductor layer; the metal oxide semiconductor layer includes a first part and a second part; the first part and the data line are connected through a first via hole; the first part is in a stripe shape; a first included angle is between extension directions of the first part and the data line; an orthographic projection of the second part overlap with an orthographic projection of the gate line on the base substrate and do not overlap with an orthographic projection of the data line on the base substrate.
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公开(公告)号：US20230352492A1
公开(公告)日：2023-11-02
申请号：US17641557
申请日：2021-03-19
Inventor： Chunping LONG , Qi QI , Wanzhi CHEN , Xinxin ZHAO
CPC classification number: H01L27/1248 , H01L25/167 , H01L33/62 , H01L33/30
Abstract: A light-emitting substrate and a display device. The light-emitting substrate includes a base substrate, an electrode layer and a definition pattern layer; the electrode layer is at a side of the base substrate, and the definition pattern layer is at a side of the electrode layer away from the base substrate; the electrode layer includes a first electrode, and the definition pattern layer covers at least a part of the first electrode; the definition pattern layer includes a plurality of first openings, the plurality of first openings expose a same first electrode. Therefore, the light-emitting substrate can ensure the bonding success rate of the light-emitting substrate, and thus can further improve the product yield of the light-emitting substrate.
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公开(公告)号：US20220276539A1
公开(公告)日：2022-09-01
申请号：US17747278
申请日：2022-05-18
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Chunping LONG , Yong QIAO , Xinyin WU
IPC: G02F1/1337 , G02F1/1343
Abstract: A method for manufacturing an array substrate includes: providing a base substrate; forming gate lines and data lines intercrossing each other, the gate lines and the data lines define multiple pixel units. Multiple pixel regions are formed in each pixel unit, a display electrode having a slit is formed in each pixel region. Each data line includes multiple data line segments. In each pixel unit, each of a part of the pixel regions has a display electrode whose slit is parallel to a data line segment adjacent to this pixel region; each of another part of the pixel regions has a display electrode whose slit is non-parallel to a data line segment adjacent to this pixel region. The display electrodes in each of the pixel units are located at a same side of the gate line to which the pixel unit where the display electrodes are located is coupled.
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公开(公告)号：US20220123028A1
公开(公告)日：2022-04-21
申请号：US17280795
申请日：2020-07-21
Inventor： Pan LI , Jianbo XIAN , Chunping LONG
IPC: H01L27/12
Abstract: The present disclosure provides an array substrate, a manufacturing method thereof, and a display device. The array substrate includes a base substrate, and a first functional layer and a second functional layer laminated one on another on the base substrate. The first functional layer forms a level-different region on the base substrate, and the second functional layer covers the level-different region. A portion of the first functional layer at the level-different region is provided with a target gradient angle, the target gradient angle is a maximum gradient angle when the second functional layer has a predetermined thickness, and the predetermined thickness is a thickness when a functional requirement of the second functional layer has been met and the second functional layer is not broken at the level-different region.
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Patent Agency Ranking
公开(公告)号：US20210408066A1
公开(公告)日：2021-12-30
申请号：US16607575
申请日：2019-01-31
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Chunping LONG
IPC: H01L27/12 , H01L29/786
Abstract: The present disclosure provides a demultiplexer, an array substrate and a display device. The array substrate comprises a plurality of data line leads, a plurality of data lines arranged side by side and the demultiplexer. The demultiplexer includes first to third control gate lines arranged in parallel and first to sixth thin film transistors. The first thin film transistor to the third thin film transistor are positioned at a side of the demultiplexer proximal to the first control gate line, the fourth thin film transistor to the sixth thin film transistor are positioned at a side of the demultiplexer proximal to the third control gate line, and drains of the first thin film transistor to the sixth thin film transistor are respectively coupled to corresponding ones of the plurality of data lines.
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公开(公告)号：US20210264836A1
公开(公告)日：2021-08-26
申请号：US17255920
申请日：2020-05-13
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Chunping LONG , Hui LI
Abstract: Provided are an array substrate and a display panel. The array substrate includes: gate lines and data lines on a substrate, the gate lines extending in a first direction, the data lines extending in a second direction, and the gate lines and the data lines crossing over each other to define pixel regions arranged in a matrix; pixel electrodes respectively in the plurality of pixel regions and on a side of the gate lines away from the substrate; common electrode lines at least partially surrounding the plurality of pixel regions; and a shielding electrode on a side of the gate lines away from the substrate and electrically connected to the common electrode lines, an orthographic projection of the shielding electrode on the substrate covering an orthographic projection of a portion, between the pixel electrodes adjacent in the second direction, of at least one of the gate lines on the substrate.
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公开(公告)号：US20210242244A1
公开(公告)日：2021-08-05
申请号：US16759016
申请日：2019-10-16
Applicant: BOE Technology Group Co., Ltd.
Inventor： Chunping LONG
IPC: H01L27/12
Abstract: An array substrate, a display panel, and a display device. The array substrate includes a substrate having a display region and a non-display region surrounding the display region. The display region includes a plurality of signal lines extending along a first direction. The non-display region includes at least three repair lead wires, and welding terminals connected to the repair lead wires in a one-to-one corresponding manner. The signal lines form overlapping regions together with an orthographic projection of at least one repair lead wire on the substrate.
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公开(公告)号：US20210215964A1
公开(公告)日：2021-07-15
申请号：US16759094
申请日：2019-10-18
Applicant: BOE Technology Group Co., Ltd.
Inventor： Chunping LONG
IPC: G02F1/1362
Abstract: The application provides a display substrate and a display device. The display substrate includes: gate lines, data lines, the gate lines and the data lines being arranged to intersect to define sub-pixels, every multiple sub-pixels in a same row constituting a pixel unit; and common electrode lines, each of the common electrode lines is between adjacent two of the gate lines. The display substrate further includes common voltage input line groups intersecting with the common electrode lines. Common voltage input lines in different groups are electrically connected to different ones of the common electrode lines, respectively; and an orthographic projection of every N columns of pixel units on a substrate covers an orthographic projection of a corresponding one of the common voltage input line groups on the substrate, where N is an integer greater than or equal to 1.
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公开(公告)号：US20210141489A1
公开(公告)日：2021-05-13
申请号：US16810092
申请日：2020-03-05
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Chunping LONG , Hui LI
IPC: G06F3/044 , G09G3/36 , G02F1/1333 , G02F1/1362
Abstract: A touch display substrate including: a base substrate having a plurality of pixel regions arranged in the form of an array; a common electrode layer on the base substrate, divided into a plurality of self-capacitive electrodes independent from each other, an orthogonal projection of each of the self-capacitive electrodes on the base substrate covering more than one of the pixel regions; a plurality of touch data lines, arranged in a different layer from the self-capacitive electrodes and each connected with a corresponding one of the self-capacitive electrodes, orthogonal projections of the touch data lines on the base substrate being located within gaps between the plurality of pixel regions; a touch detection chip, connected with each of the self-capacitive electrodes through a corresponding one of the touch data lines, and configured to load a common electrode signal to each of the self-capacitive electrodes in a display period through the corresponding touch data line, and to determine a touch position in a touch period by detecting a change in a capacitance of each of the self-capacitive electrodes through the corresponding touch data line.
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