公开(公告)号：US08069400B2

公开(公告)日：2011-11-29

申请号：US12132971

申请日：2008-06-04

申请人： Ba-Zhong Shen ,  Tak K. Lee

发明人： Ba-Zhong Shen ,  Tak K. Lee

IPC分类号： H03M13/03

CPC分类号： H04L1/0066 ,  H04L1/005 ,  H04L1/0069

摘要： Optimal circular buffer rate matching for turbo code. An offset index, δ, of 3 and a skipping index, σ, of 3 is employed in accordance with circular buffer rate matching. This allows less puncturing of information bits and more puncturing of redundancy/parity bits (e.g., which can provide for a higher rate). Multiple turbo codes may be generated from a mother code such that each generated turbo code can be employed to encode information bits. For example, a first turbo coded signal can be generated using a first turbo code generated from the mother code, and a second turbo coded signal can be generated using a second turbo code generated from the mother code. Any of these turbo coded signal can be decoded using parallel decoding processing or a single turbo decoder (when each turbo coded signal undergoes processing to transform it back to the mother code format).

摘要翻译： turbo码的最优循环缓冲率匹配。 根据循环缓冲速率匹配采用3的偏移索引δ和3的跳过索引＆sgr。 这允许更少地删除信息比特，并且更多地删除冗余/奇偶校验位（例如，其可以提供更高的速率）。 可以从母码生成多个turbo码，使得可以采用每个生成的turbo码对信息比特进行编码。 例如，可以使用从母码产生的第一turbo码生成第一turbo编码信号，并且可以使用从母码产生的第二turbo码生成第二turbo编码信号。 可以使用并行解码处理或单个turbo解码器来解码这些turbo编码信号中的任何一个（当每个turbo编码信号经历处理以将其转换回母码格式时）。

公开(公告)号：US08069387B2

公开(公告)日：2011-11-29

申请号：US12111863

申请日：2008-04-29

申请人： Ba-Zhong Shen ,  Tak K. Lee

发明人： Ba-Zhong Shen ,  Tak K. Lee

IPC分类号： H03M13/00

CPC分类号： H03M13/2957 ,  H03M13/6356 ,  H04L1/0041 ,  H04L1/0066 ,  H04L1/0067 ,  H04L1/0071

摘要： Turbo coding having combined turbo de-padding and rate matching de-padding. An approach is presented by which a singular module is operable to perform both zero bit de-padding and dummy bit de-padding in accordance with turbo encoding. Zero padding can be performed on an input information stream before undergoing turbo encoding. One or more of the 3 outputs from the turbo encoding module (e.g., systematic bits, parity 1 bits, and parity 2 bits) may then undergo dummy bit padding as well. Thereafter, these 3 streams (some or all of which may have undergone dummy bit padding) undergo sub-block interleaving. After all of these operations have taken place, a singular combined de-padding module that can be employed to perform de-padding any zero padded bits and any dummy padded bits from each of the three streams that have undergone the sub-block interleaving.

摘要翻译： Turbo编码具有组合的turbo去填充和速率匹配去填充。 提出了一种方法，通过该方法，单个模块可操作以根据turbo编码执行零比特解除填充和伪比特解除填充。 在进行turbo编码之前，可以对输入信息流执行零填充。 来自turbo编码模块的3个输出中的一个或多个（例如，系统比特，奇偶校验1比特和奇偶校验2比特）然后也可以经历伪比特填充。 此后，这3个流（其中一些或全部可能经历了伪位填充）经历子块交织。 在所有这些操作已经发生之后，可以采用单一组合的去填充模块来执行从填充子块交错的三个流中的每一个中去除任何零填充位和任何虚拟填充位。

公开(公告)号：US07831894B2

公开(公告)日：2010-11-09

申请号：US11810989

申请日：2007-06-07

申请人： Tak K. Lee ,  Ba-Zhong Shen

发明人： Tak K. Lee ,  Ba-Zhong Shen

IPC分类号： H03M13/03

CPC分类号： H03M13/2771 ,  H03M13/276 ,  H03M13/2957 ,  H03M13/6561 ,  H04L1/005 ,  H04L1/0066

摘要： Address generation for contention-free memory mappings of turbo codes with ARP (almost regular permutation) interleaves. A novel means is presented by which anticipatory address generation is employed using an index function that is based on an address mapping which corresponds to an interleave inverse order of decoding processing (π−1). In accordance with parallel turbo decoding processing, instead of performing the natural order phase decoding processing by accessing data elements from memory bank locations sequentially, the accessing of addresses is performed based on the index function that is based on an mapping and the interleave (π) employed within the turbo coding. In other words, the accessing data elements from memory bank locations is not sequential for natural order phase decoding processing. The index function also allows for the interleave (π) order phase decoding processing to be performed by accessing data elements from memory bank locations sequentially.

摘要翻译： 具有ARP（几乎规则排列）交织的turbo码的无竞争内存映射的地址生成。 提出了一种新颖的方法，其中使用基于对应于解码处理（＆pgr; -1）的交织逆顺序的地址映射的索引函数来采用预期地址生成。 根据并行turbo解码处理，代替通过从存储器单元顺序访问数据元素来执行自然次序相位解码处理，基于基于映射和交织（＆pgr）的索引函数来执行地址的访问。 ）。 换句话说，来自存储体位置的访问数据元素对于自然顺序相位解码处理不是顺序的。 索引函数还允许通过从存储体位置顺序地访问数据元素来进行交织（＆amp;）顺序相位解码处理。

公开(公告)号：US07752529B2

公开(公告)日：2010-07-06

申请号：US11493342

申请日：2006-07-26

申请人： Tak K. Lee ,  Ba-Zhong Shen

发明人： Tak K. Lee ,  Ba-Zhong Shen

IPC分类号： H03M13/00

CPC分类号： H03M13/1105 ,  H03M13/6502

摘要： Combined LDPC (Low Density Parity Check) encoder and syndrome checker. A novel approach is presented by which the encoding processing and at least a portion of the decoding processing of an LDPC coded signal can be performed using a shared circuitry. The LDPC encoding processing and syndrome calculation operations (in accordance with the LDPC decoding processing) can be performed using a common circuitry having a portion of which whose connectivity is only slightly modified depending on whether encoding or decoding is being performed. To effectuate this selection (between encoding and decoding), any of a variety of means can be employed including the use of multiplexers that are operable to select a first connectivity (for encoding) and a second connectivity (for decoding). This can result in a hardware savings of space, cost, and complexity since a shared circuitry can perform both encoding and at least part of the decoding processing.

摘要翻译： 组合LDPC（低密度奇偶校验）编码器和综合检查器。 提出了一种新颖的方法，通过该方法可以使用共享电路来执行LDPC编码信号的编码处理和至少一部分解码处理。 可以使用具有其部分连接性的公共电路来执行LDPC编码处理和校正子计算操作（根据LDPC解码处理），该部分的连接仅根据正在执行编码或解码而略微修改。 为了实现该选择（在编码和解码之间），可以采用各种手段中的任一种，包括使用可操作以选择第一连接（用于编码）和第二连接（用于解码）的多路复用器。 这可以导致空间，成本和复杂性的硬件节省，因为共享电路可以执行编码和至少部分解码处理。

公开(公告)号：US20100077277A1

公开(公告)日：2010-03-25

申请号：US12556379

申请日：2009-09-09

申请人： Ba-Zhong Shen ,  Tak K. Lee

发明人： Ba-Zhong Shen ,  Tak K. Lee

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： H03M13/116 ,  H03M13/033 ,  H03M13/1137 ,  H03M13/118 ,  H03M13/1185 ,  H03M13/635 ,  H03M13/6516 ,  H03M13/6527 ,  H03M13/6544 ,  H03M13/6561

摘要： Multi-CSI (Cyclic Shifted Identity) sub-matrix based LDPC (Low Density Parity Check) codes. A CSI parameter set, that includes at least one dual-valued entry and may also include at least one single-valued entry, and/or at least one all-zero-valued entry, is employed to generate an LDPC matrix. One of the single-valued entries may be 0 (being used to generate a CSI matrix with cyclic shift value of 0, corresponding to an identity sub-matrix such that all entries along the diagonal have elements values of 1, and all other elements therein are 0). Once the LDPC matrix is generated, it is employed to decode an LDPC coded signal to make an estimate of an information bit encoded therein. Also, the LDPC matrix may itself be used as an LDPC generator matrix (or the LDPC generator matrix may alternatively be generated by processing the LDPC matrix) for use in encoding an information bit.

摘要翻译： 多CSI（循环移位身份）基于子矩阵的LDPC（低密度奇偶校验）码。 使用包括至少一个双值条目并且还可以包括至少一个单值条目和/或至少一个全零值条目的CSI参数集合来生成LDPC矩阵。 单值条目中的一个可以是0（用于生成具有循环移位值0的CSI矩阵，对应于身份子矩阵，使得沿着对角线的所有条目具有元素值1，并且其中所有其他元素 是0）。 一旦生成了LDPC矩阵，就采用LDPC编码信号进行解码，对其中编码的信息比特进行估计。 此外，LDPC矩阵本身可以用作LDPC生成器矩阵（或者可替换地，LDPC生成器矩阵可以通过处理LDPC矩阵来生成）用于对信息比特进行编码。

公开(公告)号：US07631246B2

公开(公告)日：2009-12-08

申请号：US11417316

申请日：2006-05-03

申请人： Ba-Zhong Shen ,  Tak K. Lee ,  Kelly Brian Cameron

发明人： Ba-Zhong Shen ,  Tak K. Lee ,  Kelly Brian Cameron

IPC分类号： H03M13/35

CPC分类号： H03M13/116 ,  H03M13/1185 ,  H03M13/1188 ,  H03M13/618 ,  H03M13/6362

摘要： LDPC (Low Density Parity Check) code size adjustment by shortening and puncturing. A variety of LDPC coded signals may be generated from an initial LDPC code using selected shortening and puncturing. Using LDPC code size adjustment approach, a single communication device whose hardware design is capable of processing the original LDPC code is also capable to process the various other LDPC codes constructed from the original LDPC code after undergoing appropriate shortening and puncturing. This provides significant design simplification and reduction in complexity because the same hardware can be implemented to accommodate the various LDPC codes generated from the original LDPC code. Therefore, a multi-LDPC code capable communication device can be implemented that is capable to process several of the generated LDPC codes. This approach allows for great flexibility in the LDPC code design, in that, the original code rate can be maintained after performing the shortening and puncturing.

摘要翻译： LDPC（低密度奇偶校验）码字大小调整通过缩短和删截。 可以使用选择的缩短和删截从初始LDPC码生成各种LDPC编码信号。 使用LDPC码大小调整方法，硬件设计能够处理原始LDPC码的单个通信设备也能够在进行适当的缩短和删截之后处理由原始LDPC码构成的各种其他LDPC码。 这提供了重要的设计简化和复杂性的降低，因为可以实现相同的硬件以适应从原始LDPC码产生的各种LDPC码。 因此，可以实现能够处理几个所生成的LDPC码的具有多LDPC码的通信装置。 这种方法允许在LDPC码设计中具有极大的灵活性，因为可以在执行缩短和删截之后维持原始码率。

公开(公告)号：US07617433B2

公开(公告)日：2009-11-10

申请号：US11360268

申请日：2006-02-23

申请人： Tak K. Lee ,  Hau Thien Tran ,  Ba-Zhong Shen ,  Kelly Brian Cameron

发明人： Tak K. Lee ,  Hau Thien Tran ,  Ba-Zhong Shen ,  Kelly Brian Cameron

IPC分类号： H03M13/00

CPC分类号： H03M13/116 ,  H03M13/1137 ,  H03M13/255 ,  H03M13/27 ,  H03M13/6362 ,  H03M13/6566

摘要： Implementation of LDPC (Low Density Parity Check) decoder by sweeping through sub-matrices. A novel approach is presented by which an LDPC coded signal is decoded processing the columns and rows of the individual sub-matrices of the low density parity check matrix corresponding to the LDPC code. The low density parity check matrix can partitioned into rows and columns according to each of the sub-matrices of it, and each of those sub-matrices also includes corresponding rows and columns. For example, when performing bit node processing, the same columns of at 1 or more sub-matrices can be processed together (e.g., all 1st columns in 1 or more sub-matrices, all 2nd columns in 1 or more sub-matrices, etc.). Analogously, when performing check node processing, the same rows of 1 or more sub-matrices can be processed together (e.g., all 1st rows in 1 or more sub-matrices, all 2nd rows in 1 or more sub-matrices, etc.).

摘要翻译： 通过扫描子矩阵实现LDPC（低密度奇偶校验）解码器。 提出了一种解码处理与LDPC码对应的低密度奇偶校验矩阵的各个子矩阵的列和行的LDPC编码信号的新方法。 低密度奇偶校验矩阵可以根据它的每个子矩阵划分成行和列，并且这些子矩阵中的每一个也包括相应的行和列。 例如，当执行位节点处理时，可以一起处理1个或更多个子矩阵的相同列（例如，1个或更多个子矩阵中的所有第1列，1个或更多个子矩阵中的所有第2列等 。）。 类似地，当执行校验节点处理时，可以一起处理1个或更多个子矩阵的相同行（例如，1个或更多个子矩阵中的所有第1行，1个或更多个子矩阵中的所有第2行等） 。

公开(公告)号：US20090063940A1

公开(公告)日：2009-03-05

申请号：US11860679

申请日：2007-09-25

申请人： Johnson Yen ,  Ba-Zhong Shen ,  Tak K. Lee

发明人： Johnson Yen ,  Ba-Zhong Shen ,  Tak K. Lee

IPC分类号： H03M13/41

CPC分类号： H03M13/3955 ,  H03M13/4107 ,  H03M13/4146

摘要： A means is presented by which two trellis stages can be processes simultaneously and in parallel with one another (e.g., during a single clock cycle) thereby significantly increasing data throughput. Any one or more modules within a REX module can be implemented using a radix-4 architecture to increase data throughput. For example, any or more of a SMU (Survivor Memory Unit), a PED (Path Equivalency Detector), and a RMU (Reliability Measure Unit) can be implemented in accordance with the principles of radix-4 decoding processing.

摘要翻译： 提出了一种手段，其中两个网格级可以是彼此同时和并行处理（例如，在单个时钟周期内），从而显着增加数据吞吐量。 REX模块中的任何一个或多个模块可以使用基数4架构来实现，以增加数据吞吐量。 例如，可以根据基数-4解码处理的原理来实现SMU（幸存者存储器单元），PED（路径等效性检测器）和RMU（可靠性测量单元）中的任何一个或多个。

公开(公告)号：US20080092018A1

公开(公告)日：2008-04-17

申请号：US11586101

申请日：2006-10-25

申请人： Ba-Zhong Shen ,  Tak K. Lee

发明人： Ba-Zhong Shen ,  Tak K. Lee

IPC分类号： H03M13/00

CPC分类号： H03M13/2996 ,  H03M13/2993

摘要： Tail-biting turbo code for arbitrary number of information bits. A novel means is presented in which, for most cases, no extra symbols at all need to be padded to an input sequence to ensure that a turbo encoder operates according to tail-biting (i.e., where the beginning and ending state of the turbo encoder is the same). In a worst case scenario, only a single symbol (or a single bit) needs to be padded to the input sequence. Herein, all of the input bits of the input sequence are interleaved within the turbo encoding. In the instance where the at most one symbol (or at most one bit) needs to be padded to the input sequence, then that at most one symbol (or one bit) is also interleaved within the turbo encoding. Moreover, any size of an input sequence can be accommodated using the means herein to achieve tail-biting.

摘要翻译： 尾随Turbo码用于任意数量的信息位。 提出了一种新颖的方法，其中在大多数情况下，根本不需要将额外的符号填充到输入序列，以确保turbo编码器根据尾巴（即，其中turbo编码器的开始和结束状态 是一样的）。 在最坏的情况下，只需要将一个符号（或一个位）填充到输入序列中。 这里，输入序列的所有输入比特在Turbo编码中进行交织。 在最多一个符号（或最多一位）需要被填充到输入序列的情况下，那么在turbo编码中最多一个符号（或一个比特）也被交织。 此外，使用这里的手段可以适应任何大小的输入序列以实现尾巴咬合。

公开(公告)号：US08572469B2

公开(公告)日：2013-10-29

申请号：US12915936

申请日：2010-10-29

申请人： Tak K. Lee ,  Ba-Zhong Shen

发明人： Tak K. Lee ,  Ba-Zhong Shen

IPC分类号： H03M13/03

CPC分类号： G06F11/1008 ,  H03M13/2753 ,  H03M13/2775 ,  H03M13/2957 ,  H03M13/3905 ,  H03M13/3972

摘要： Turbo decoder employing ARP (almost regular permutation) interleave and arbitrary number of decoding processors. A novel approach is presented herein by which an arbitrarily selected number (M) of decoding processors (e.g., a plurality of parallel implemented turbo decoders) be employed to perform decoding of a turbo coded signal while still using a selected embodiment of an ARP (almost regular permutation) interleave. The desired number of decoding processors is selected, and very slight modification of an information block (thereby generating a virtual information block) is made to accommodate that virtual information block across all of the decoding processors during all decoding cycles except some dummy decoding cycles. In addition, contention-free memory mapping is provided between the decoding processors (e.g., a plurality of turbo decoders) and memory banks (e.g., a plurality of memories).

摘要翻译： Turbo解码器采用ARP（几乎规则排列）交错和任意数量的解码处理器。 本文提出了一种新颖的方法，通过该方法，使用任意选择的数量（M）的解码处理器（例如，多个并行实现的turbo解码器）来执行turbo编码信号的解码，同时仍然使用所选择的ARP实施例（几乎 正则排列）交错。 选择所需数量的解码处理器，并且进行信息块（从而生成虚拟信息块）的非常轻微的修改以在除了一些虚拟解码周期之外的所有解码周期期间在所有解码处理器之间容纳该虚拟信息块。 此外，在解码处理器（例如，多个turbo解码器）和存储体（例如，多个存储器）之间提供无竞争的存储器映射。