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41.发明授权公开(公告)号：US06807608B2
公开(公告)日：2004-10-19
申请号：US10077560
申请日：2002-02-15
申请人： Victor Roberts Augsburg , James Norris Dieffenderfer , Bernard Charles Drerup , Richard Gerard Hofmann , Thomas Andrew Sartorius , Barry Joe Wolford
发明人： Victor Roberts Augsburg , James Norris Dieffenderfer , Bernard Charles Drerup , Richard Gerard Hofmann , Thomas Andrew Sartorius , Barry Joe Wolford
IPC分类号： G06F1200
CPC分类号： G06F12/0831 , Y02D10/13
摘要： A method and system for performing variable-sized memory coherency transactions. A bus interface unit coupled between a slave and a master may be configured to receive a request (master request) comprising a plurality of coherency granules from the master. Each snooping unit in the system may be configured to snoop a different number of coherency granules in the master request at a time. Once the bus interface unit has received a collection of sets of indications from each snooping logic unit indicating that the associated collection of coherency granules in the master request have been snooped by each snooping unit and that the data at the addresses for the collection of coherency granules snooped has not been updated, the bus interface unit may allow the data at the addresses of those coherency granules not updated to be transferred between the requesting master and the slave.
摘要翻译： 用于执行可变大小的存储器一致性事务的方法和系统。 耦合在从机和主机之间的总线接口单元可以被配置为从主机接收包括多个相干性颗粒的请求（主请求）。 系统中的每个窥探单元可以被配置为一次窥探主请求中的不同数量的一致性粒子。 一旦总线接口单元已经从每个窥探逻辑单元接收到指示集合的指示集合，指示主请求中的相关性集合的集合已被每个监听单元窥探，并且用于收集相关性颗粒的地址上的数据 被侦听未被更新，总线接口单元可以允许未更新的那些一致性粒度的地址上的数据在请求主机和从机之间传送。
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42.发明授权Method and system for executing a non-native stack-based instruction within a computer system 失效用于在计算机系统内执行非本机堆栈指令的方法和系统
公开(公告)号：US5898885A
公开(公告)日：1999-04-27
申请号：US829024
申请日：1997-03-31
CPC分类号： G06F9/30174 , G06F9/30134 , G06F9/45504
摘要： A method and system for executing a non-native stack-based instruction within a computer system is disclosed. In accordance with the method and system of the present invention, a computer system capable of executing a set of non-native stack-access instructions is provided which includes a system memory, an instruction set convertor, and a processor. The system memory is utilized to store the non-native stack-access instructions, and part of the system memory is utilized as a stack. The instruction set convertor is utilized to convert the non-native stack-access instructions to a set of native instructions. When encountering a block of non-native stack-access instructions which include paired push and pop stack operations, the instruction set convertor produces a set of native instructions that ignores paired push and pop stack operations and retains all relevant number values in general purpose registers. The processor then processes the native instructions from the instruction set convertor, in which the immediate paired push and pop operations are eliminated.
摘要翻译： 公开了一种用于在计算机系统内执行非本机堆栈指令的方法和系统。 根据本发明的方法和系统，提供一种能够执行一组非本地堆栈访问指令的计算机系统，其包括系统存储器，指令集转换器和处理器。 系统存储器用于存储非本地堆栈访问指令，并且系统存储器的一部分被用作堆栈。 指令集转换器用于将非本地堆栈访问指令转换为一组本机指令。 当遇到一组非本地堆栈访问指令（包括配对的push和pop stack操作）时，指令集转换器产生一组本机指令，忽略配对的push和pop栈操作，并将所有相关数值保留在通用寄存器中。 然后，处理器处理来自指令集转换器的本机指令，其中立即配对的推送和弹出操作被消除。
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公开(公告)号：US08095720B2
公开(公告)日：2012-01-10
申请号：US12986263
申请日：2011-01-07
CPC分类号： G06F13/4027
摘要： The present invention provides for a system comprising a peripheral component interface (PCI) host bridge. The PCI host bridge is configured to be coupled to a PCI bus, and to receive a system reset signal, to generate a PCI bus reset signal based on the received system reset signal, to detect a PCI operational mode of the PCI bus, and to generate a voltage indicator signal based on the detected PCI operational mode. A voltage regulator is coupled to the PCI host bridge and configured to receive the voltage indicator signal and to regulate a signaling voltage for the PCI bus based on the voltage indicator signal.
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公开(公告)号：US20110107000A1
公开(公告)日：2011-05-05
申请号：US12986263
申请日：2011-01-07
IPC分类号： G06F13/36
CPC分类号： G06F13/4027
摘要： The present invention provides for a system comprising a peripheral component interface (PCI) host bridge. The PCI host bridge is configured to be coupled to a PCI bus, and to receive a system reset signal, to generate a PCI bus reset signal based on the received system reset signal, to detect a PCI operational mode of the PCI bus, and to generate a voltage indicator signal based on the detected PCI operational mode. A voltage regulator is coupled to the PCI host bridge and configured to receive the voltage indicator signal and to regulate a signaling voltage for the PCI bus based on the voltage indicator signal.
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公开(公告)号：US07934042B2
公开(公告)日：2011-04-26
申请号：US10965628
申请日：2004-10-14
CPC分类号： G06F13/4027
摘要： The present invention provides for a system comprising a peripheral component interface (PCI) host bridge. The PCI host bridge is configured to be coupled to a PCI bus, and to receive a system reset signal, to generate a PCI bus reset signal based on the received system reset signal, to detect a PCI operational mode of the PCI bus, and to generate a voltage indicator signal based on the detected PCI operational mode. A voltage regulator is coupled to the PCI host bridge and configured to receive the voltage indicator signal and to regulate a signaling voltage for the PCI bus based on the voltage indicator signal.
摘要翻译： 本发明提供一种包括外围组件接口（PCI）主机桥的系统。 PCI主机桥被配置为耦合到PCI总线，并且接收系统复位信号，以基于接收到的系统复位信号产生PCI总线复位信号，以检测PCI总线的PCI操作模式，并且 基于检测到的PCI操作模式生成电压指示器信号。 电压调节器耦合到PCI主机桥，并被配置为接收电压指示器信号并且基于电压指示器信号来调节用于PCI总线的信令电压。
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公开(公告)号：US20100169527A1
公开(公告)日：2010-07-01
申请号：US12719683
申请日：2010-03-08
IPC分类号： G06F13/00
CPC分类号： G06F13/4022
摘要： An apparatus is described for data processing in a computer system. The apparatus comprises a data processing device having a data processing master, a functionally coupled data processor core, and a functionally coupled data processor slave. Both the data processing master and the data processing slave are coupled to a common bus or common crossbar switch. The data processing device processes the data associated with transfers to or from the data processor slave. System masters will direct transactions that require data processing to the data processing slave, which will indirectly interact with the target memory slave. System masters will direct transactions that do not require data processing, directly to the target memory slave.
摘要翻译： 描述了一种用于计算机系统中的数据处理的装置。 该装置包括具有数据处理主机，功能耦合的数据处理器核心和功能耦合的数据处理器从机的数据处理设备。 数据处理主机和数据处理从机都耦合到公共总线或公共交叉开关。 数据处理设备处理与传送到数据处理器从站或从数据处理器从站传输相关联的数据。 系统主人将将需要数据处理的事务指向数据处理从站，这将与目标存储器从站间接交互。 系统主人将直接向目标内存从站直接进行不需要数据处理的事务。
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公开(公告)号：US07707347B2
公开(公告)日：2010-04-27
申请号：US12353299
申请日：2009-01-14
IPC分类号： G06F13/36
CPC分类号： G06F13/4022
摘要： An apparatus is described for data processing in a computer system. The apparatus comprises a data processing device having a data processing master, a functionally coupled data processor core, and a functionally coupled data processor slave. Both the data processing master and the data processing slave are coupled to a common bus or common crossbar switch. The data processing device processes the data associated with transfers to or from the data processor slave. System masters will direct transactions that require data processing to the data processing slave, which will indirectly interact with the target memory slave. System masters will direct transactions that do not require data processing, directly to the target memory slave.
摘要翻译： 描述了一种用于计算机系统中的数据处理的装置。 该装置包括具有数据处理主机，功能耦合的数据处理器核心和功能耦合的数据处理器从机的数据处理设备。 数据处理主机和数据处理从机都耦合到公共总线或公共交叉开关。 数据处理设备处理与传送到数据处理器从站或从数据处理器从站传输相关联的数据。 系统主人将将需要数据处理的事务指向数据处理从站，这将与目标存储器从站间接交互。 系统主人将直接向目标内存从站直接进行不需要数据处理的事务。
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48.发明授权Data communication method and apparatus utilizing credit-based data transfer protocol and credit loss detection mechanism 失效数据通信方法和设备利用信用数据传输协议和信用损失检测机制公开(公告)号：US07647435B2
公开(公告)日：2010-01-12
申请号：US11761154
申请日：2007-06-11
CPC分类号： G06F13/36
摘要： A communications bus for a digital device includes a credit-based flow control mechanism, in which a sending component maintains a local record of its credits. Credits are returned to the sender by pulsing a single-bit credit return line. A separate mechanism provides a count of available credits from the receiver, the separate mechanism not necessarily being current. The local record is compared to the count of credits from the separate mechanism over a pre-determined time interval, failure of the two values to agree at any time during the interval indicating a probable credit discrepancy. A credit discrepancy is confirmed, preferably by suspending certain bus activity for a sufficiently long period to account for any delay in propagating credit value changes, and re-comparing the values. Preferably, the bus communicates between internal components of an integrated circuit chip.
摘要翻译： 用于数字设备的通信总线包括基于信用的流量控制机制，其中发送组件保持其信用的本地记录。 通过脉冲单位信用回报线将积分返还给发送方。 单独的机制提供来自接收器的可用信用的计数，单独的机制不一定是当前的。 将本地记录与预定时间间隔内的单独机制的信用计数进行比较，两个值在表示可能的信用差异的间隔期间的任何时间失败。 确认信用差异，最好是通过暂停一段长时间的公共汽车活动来解决传播信用额度变化的任何延误，并重新比较价值。 优选地，总线在集成电路芯片的内部部件之间进行通信。
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公开(公告)号：US07526595B2
公开(公告)日：2009-04-28
申请号：US10202722
申请日：2002-07-25
IPC分类号： G06F13/36
CPC分类号： G06F13/4022
摘要： An apparatus and method is described for data processing in a computer system. The apparatus comprises a data processing device having a data processing master, a functionally coupled data processor core, and a functionally coupled data processor slave. Both the data processing master and the data processing slave are coupled to a common bus or common crossbar switch. The data processing device processes the data associated with transfers to or from the data processor slave. System masters will direct transactions that require data processing to the data processing slave, which will indirectly interact with the target memory slave. System masters will direct transactions that do not require data processing, directly to the target memory slave.
摘要翻译： 描述了用于计算机系统中的数据处理的装置和方法。 该装置包括具有数据处理主机，功能耦合的数据处理器核心和功能耦合的数据处理器从机的数据处理设备。 数据处理主机和数据处理从机都耦合到公共总线或公共交叉开关。 数据处理设备处理与传送到数据处理器从站或从数据处理器从站传输相关联的数据。 系统主人将将需要数据处理的事务指向数据处理从站，这将与目标存储器从站间接交互。 系统主人将直接向目标内存从站直接进行不需要数据处理的事务。
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50.发明授权System on a chip bus with automatic pipeline stage insertion for timing closure 失效系统具有自动流水线插入的片上总线，用于定时关闭公开(公告)号：US07296175B2
公开(公告)日：2007-11-13
申请号：US10971947
申请日：2004-10-22
申请人： Victor Roberts Augsburg , James Norris Dieffenderfer , Bernard Charles Drerup , Richard Gerard Hofmann , Thomas Andrew Sartorius , Barry Joe Wolford
发明人： Victor Roberts Augsburg , James Norris Dieffenderfer , Bernard Charles Drerup , Richard Gerard Hofmann , Thomas Andrew Sartorius , Barry Joe Wolford
CPC分类号： G06F17/5045
摘要： A method of designing a system on a chip (SoC) to operate with varying latencies and frequencies. A layout of the chip is designed with specific placement of devices, including a bus controller, initiator, and target devices. The time for a signal to propagate from a source device to a destination device is determined relative to a default propagation time. A pipeline stage is then inserted into a bus path between said source device and destination device for each additional time the signal takes to propagate. Each device (i.e., initiators, targets, and bus controller) is designed with logic to control a protocol that functions with a variety of response latencies. With the additional logic, the devices do not need to be changed when pipeline stages are inserted in the various paths. Registers are utilized as the pipeline stages that are inserted within the paths.
摘要翻译： 一种设计芯片上的系统（SoC）以在不同的延迟和频率下工作的方法。 芯片的布局设计具有特定的器件布局，包括总线控制器，启动器和目标器件。 相对于默认传播时间确定信号从源设备传播到目的地设备的时间。 然后，在信号需要传播的每个附加时间，将流水线级插入到所述源设备和目的设备之间的总线路径中。 每个设备（即，启动器，目标和总线控制器）被设计为具有控制以各种响应延迟起作用的协议的逻辑。 使用附加逻辑，当管道级插入各种路径时，不需要更改设备。 寄存器被用作插入到路径内的流水线级。
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