-
公开(公告)号：US07707347B2
公开(公告)日：2010-04-27
申请号：US12353299
申请日：2009-01-14
IPC分类号： G06F13/36
CPC分类号： G06F13/4022
摘要： An apparatus is described for data processing in a computer system. The apparatus comprises a data processing device having a data processing master, a functionally coupled data processor core, and a functionally coupled data processor slave. Both the data processing master and the data processing slave are coupled to a common bus or common crossbar switch. The data processing device processes the data associated with transfers to or from the data processor slave. System masters will direct transactions that require data processing to the data processing slave, which will indirectly interact with the target memory slave. System masters will direct transactions that do not require data processing, directly to the target memory slave.
摘要翻译： 描述了一种用于计算机系统中的数据处理的装置。 该装置包括具有数据处理主机，功能耦合的数据处理器核心和功能耦合的数据处理器从机的数据处理设备。 数据处理主机和数据处理从机都耦合到公共总线或公共交叉开关。 数据处理设备处理与传送到数据处理器从站或从数据处理器从站传输相关联的数据。 系统主人将将需要数据处理的事务指向数据处理从站，这将与目标存储器从站间接交互。 系统主人将直接向目标内存从站直接进行不需要数据处理的事务。
-
公开(公告)号：US07526595B2
公开(公告)日：2009-04-28
申请号：US10202722
申请日：2002-07-25
IPC分类号： G06F13/36
CPC分类号： G06F13/4022
摘要： An apparatus and method is described for data processing in a computer system. The apparatus comprises a data processing device having a data processing master, a functionally coupled data processor core, and a functionally coupled data processor slave. Both the data processing master and the data processing slave are coupled to a common bus or common crossbar switch. The data processing device processes the data associated with transfers to or from the data processor slave. System masters will direct transactions that require data processing to the data processing slave, which will indirectly interact with the target memory slave. System masters will direct transactions that do not require data processing, directly to the target memory slave.
摘要翻译： 描述了用于计算机系统中的数据处理的装置和方法。 该装置包括具有数据处理主机，功能耦合的数据处理器核心和功能耦合的数据处理器从机的数据处理设备。 数据处理主机和数据处理从机都耦合到公共总线或公共交叉开关。 数据处理设备处理与传送到数据处理器从站或从数据处理器从站传输相关联的数据。 系统主人将将需要数据处理的事务指向数据处理从站，这将与目标存储器从站间接交互。 系统主人将直接向目标内存从站直接进行不需要数据处理的事务。
-
公开(公告)号：US07003064B2
公开(公告)日：2006-02-21
申请号：US10042098
申请日：2002-01-07
CPC分类号： H03L7/06 , G06F1/12 , H04L7/0008 , H04L7/02
摘要： In one form, apparatus for aligning clock signals includes first and second logic circuitry for receiving respective first and second clock signals. The first and second clock signals are substantially synchronized and operations of the first logic circuitry and second logic circuitry are clocked by the respective first and second clock signals. The first logic circuitry receives a third clock signal derived from the second clock signal, and by repeatedly sampling the third clock signal with the first clock signal, the first logic circuitry repeatedly detects relative phase relations of the first and third clock signals. The second logic circuitry adjusts the phase of the third clock signal responsive to an accumulation of the phase relation detecting.
-
4.发明授权Method and system for executing a non-native stack-based instruction within a computer system 失效用于在计算机系统内执行非本机堆栈指令的方法和系统
公开(公告)号：US5898885A
公开(公告)日：1999-04-27
申请号：US829024
申请日：1997-03-31
CPC分类号： G06F9/30174 , G06F9/30134 , G06F9/45504
摘要： A method and system for executing a non-native stack-based instruction within a computer system is disclosed. In accordance with the method and system of the present invention, a computer system capable of executing a set of non-native stack-access instructions is provided which includes a system memory, an instruction set convertor, and a processor. The system memory is utilized to store the non-native stack-access instructions, and part of the system memory is utilized as a stack. The instruction set convertor is utilized to convert the non-native stack-access instructions to a set of native instructions. When encountering a block of non-native stack-access instructions which include paired push and pop stack operations, the instruction set convertor produces a set of native instructions that ignores paired push and pop stack operations and retains all relevant number values in general purpose registers. The processor then processes the native instructions from the instruction set convertor, in which the immediate paired push and pop operations are eliminated.
摘要翻译： 公开了一种用于在计算机系统内执行非本机堆栈指令的方法和系统。 根据本发明的方法和系统，提供一种能够执行一组非本地堆栈访问指令的计算机系统，其包括系统存储器，指令集转换器和处理器。 系统存储器用于存储非本地堆栈访问指令，并且系统存储器的一部分被用作堆栈。 指令集转换器用于将非本地堆栈访问指令转换为一组本机指令。 当遇到一组非本地堆栈访问指令（包括配对的push和pop stack操作）时，指令集转换器产生一组本机指令，忽略配对的push和pop栈操作，并将所有相关数值保留在通用寄存器中。 然后，处理器处理来自指令集转换器的本机指令，其中立即配对的推送和弹出操作被消除。
-
公开(公告)号：US06819726B2
公开(公告)日：2004-11-16
申请号：US09732000
申请日：2000-12-07
IPC分类号： H03K514
摘要： The invention includes a circuit for aligning the phase of a clock derived from a frequency multiplied version of a reference clock used in a computer system. The dynamic phase alignment circuit includes a few logic gates to perform the operation of delaying the derived clock, detecting its phase misalignment, and correcting such misalignment by incrementally aligning the phase of the derived clock to the reference clock. The invention is capable of aligning the phase of a derived clock to a reference clock in a computer system whose CPU operates at as high a frequency as about 500 MHz or higher.
摘要翻译： 本发明包括用于对准从在计算机系统中使用的参考时钟的倍增版本导出的时钟的相位的电路。 动态相位对准电路包括几个逻辑门，用于执行延迟导出时钟的操作，检测其相位未对准，以及通过将导出的时钟的相位逐渐对准到参考时钟来校正这种不对准。 本发明能够将得到的时钟的相位与计算机系统中的基准时钟对准，该计算机系统的CPU以高于约500MHz或更高的频率工作。
-
-
-
-
搜索结果
5 条记录 (耗时 0.017 秒)
