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公开(公告)号：US20090132743A1
公开(公告)日：2009-05-21
申请号：US12353299
申请日：2009-01-14
IPC分类号： G06F13/40
CPC分类号： G06F13/4022
摘要： An apparatus is described for data processing in a computer system. The apparatus comprises a data processing device having a data processing master, a functionally coupled data processor core, and a functionally coupled data processor slave. Both the data processing master and the data processing slave are coupled to a common bus or common crossbar switch. The data processing device processes the data associated with transfers to or from the data processor slave. System masters will direct transactions that require data processing to the data processing slave, which will indirectly interact with the target memory slave. System masters will direct transactions that do not require data processing, directly to the target memory slave.
摘要翻译： 描述了一种用于计算机系统中的数据处理的装置。 该装置包括具有数据处理主机，功能耦合的数据处理器核心和功能耦合的数据处理器从机的数据处理设备。 数据处理主机和数据处理从机都耦合到公共总线或公共交叉开关。 数据处理设备处理与传送到数据处理器从站或从数据处理器从站传输相关联的数据。 系统主人将将需要数据处理的事务指向数据处理从站，这将与目标存储器从站间接交互。 系统主人将直接向目标内存从站直接进行不需要数据处理的事务。
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公开(公告)号：US20100169527A1
公开(公告)日：2010-07-01
申请号：US12719683
申请日：2010-03-08
IPC分类号： G06F13/00
CPC分类号： G06F13/4022
摘要： An apparatus is described for data processing in a computer system. The apparatus comprises a data processing device having a data processing master, a functionally coupled data processor core, and a functionally coupled data processor slave. Both the data processing master and the data processing slave are coupled to a common bus or common crossbar switch. The data processing device processes the data associated with transfers to or from the data processor slave. System masters will direct transactions that require data processing to the data processing slave, which will indirectly interact with the target memory slave. System masters will direct transactions that do not require data processing, directly to the target memory slave.
摘要翻译： 描述了一种用于计算机系统中的数据处理的装置。 该装置包括具有数据处理主机，功能耦合的数据处理器核心和功能耦合的数据处理器从机的数据处理设备。 数据处理主机和数据处理从机都耦合到公共总线或公共交叉开关。 数据处理设备处理与传送到数据处理器从站或从数据处理器从站传输相关联的数据。 系统主人将将需要数据处理的事务指向数据处理从站，这将与目标存储器从站间接交互。 系统主人将直接向目标内存从站直接进行不需要数据处理的事务。
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公开(公告)号：US07707347B2
公开(公告)日：2010-04-27
申请号：US12353299
申请日：2009-01-14
IPC分类号： G06F13/36
CPC分类号： G06F13/4022
摘要： An apparatus is described for data processing in a computer system. The apparatus comprises a data processing device having a data processing master, a functionally coupled data processor core, and a functionally coupled data processor slave. Both the data processing master and the data processing slave are coupled to a common bus or common crossbar switch. The data processing device processes the data associated with transfers to or from the data processor slave. System masters will direct transactions that require data processing to the data processing slave, which will indirectly interact with the target memory slave. System masters will direct transactions that do not require data processing, directly to the target memory slave.
摘要翻译： 描述了一种用于计算机系统中的数据处理的装置。 该装置包括具有数据处理主机，功能耦合的数据处理器核心和功能耦合的数据处理器从机的数据处理设备。 数据处理主机和数据处理从机都耦合到公共总线或公共交叉开关。 数据处理设备处理与传送到数据处理器从站或从数据处理器从站传输相关联的数据。 系统主人将将需要数据处理的事务指向数据处理从站，这将与目标存储器从站间接交互。 系统主人将直接向目标内存从站直接进行不需要数据处理的事务。
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公开(公告)号：US07526595B2
公开(公告)日：2009-04-28
申请号：US10202722
申请日：2002-07-25
IPC分类号： G06F13/36
CPC分类号： G06F13/4022
摘要： An apparatus and method is described for data processing in a computer system. The apparatus comprises a data processing device having a data processing master, a functionally coupled data processor core, and a functionally coupled data processor slave. Both the data processing master and the data processing slave are coupled to a common bus or common crossbar switch. The data processing device processes the data associated with transfers to or from the data processor slave. System masters will direct transactions that require data processing to the data processing slave, which will indirectly interact with the target memory slave. System masters will direct transactions that do not require data processing, directly to the target memory slave.
摘要翻译： 描述了用于计算机系统中的数据处理的装置和方法。 该装置包括具有数据处理主机，功能耦合的数据处理器核心和功能耦合的数据处理器从机的数据处理设备。 数据处理主机和数据处理从机都耦合到公共总线或公共交叉开关。 数据处理设备处理与传送到数据处理器从站或从数据处理器从站传输相关联的数据。 系统主人将将需要数据处理的事务指向数据处理从站，这将与目标存储器从站间接交互。 系统主人将直接向目标内存从站直接进行不需要数据处理的事务。
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5.发明授权System and method for providing improved bus utilization via target directed completion 失效通过目标定向完成提供改进的总线利用率的系统和方法公开(公告)号：US06973520B2
公开(公告)日：2005-12-06
申请号：US10195172
申请日：2002-07-11
申请人： Bernard Charles Drerup , Jaya Prakash Subramaniam Ganasan , Richard Gerard Hofmann , Richard Nicholas Iachetta, Jr. , Barry Joe Wolford
发明人： Bernard Charles Drerup , Jaya Prakash Subramaniam Ganasan , Richard Gerard Hofmann , Richard Nicholas Iachetta, Jr. , Barry Joe Wolford
IPC分类号： G06F13/00 , G06F13/14 , G06F13/364
CPC分类号： G06F13/364
摘要： An electronic system is disclosed, including multiple initiators and one or more targets coupled to a bus, and a request mask control unit (RMCU). The initiators are configured to initiate requests (e.g., read requests and write requests) via the bus, and the targets are configured to receive requests from the initiators via the bus. The targets are also configured to produce multiple MaskEnable signals, wherein each of the MaskEnable signals is generated following an initial request received via the bus, and dependent on a corresponding “masking situation” within the target. The RMCU receives the MaskEnable signals and produces multiple RequestMask signals dependent upon the MaskEnable signals. One or more of the initiators are permitted to repeat requests via the bus dependent upon one or more of the RequestMask signals. This mechanism provides additional bus bandwidth for carrying out successful data transfers.
摘要翻译： 公开了一种电子系统，包括多个启动器和耦合到总线的一个或多个目标，以及请求掩码控制单元（RMCU）。 启动器被配置为经由总线发起请求（例如，读请求和写请求），并且目标被配置为经由总线接收来自发起者的请求。 目标还被配置为产生多个MaskEnable信号，其中每个MaskEnable信号是在经由总线接收到的初始请求之后生成的，并且取决于目标内相应的“屏蔽情况”。 RMCU接收MaskEnable信号，并根据MaskEnable信号产生多个RequestMask信号。 一个或多个启动器被允许经由总线重复请求，取决于一个或多个请求掩码信号。 该机制为进行成功的数据传输提供了额外的总线带宽。
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6.发明授权System on a chip bus with automatic pipeline stage insertion for timing closure 有权系统具有自动流水线插入的片上总线，用于定时关闭公开(公告)号：US06834378B2
公开(公告)日：2004-12-21
申请号：US10264162
申请日：2002-10-03
申请人： Victor Roberts Augsburg , James Norris Dieffenderfer , Bernard Charles Drerup , Richard Gerard Hofmann , Thomas Andrew Sartorius , Barry Joe Wolford
发明人： Victor Roberts Augsburg , James Norris Dieffenderfer , Bernard Charles Drerup , Richard Gerard Hofmann , Thomas Andrew Sartorius , Barry Joe Wolford
IPC分类号： G06F945
CPC分类号： G06F17/5045
摘要： A method of designing a system on a chip (SoC) to operate with varying latencies and frequencies. A layout of the chip is designed with specific placement of devices, including a bus controller, initiator, and target devices. The time for a signal to propagate from a source device to a destination device is determined relative to a default propagation time. A pipeline stage is then inserted into a bus path between said source device and destination device for each additional time the signal takes to propagate. Each device (i.e., initiators, targets, and bus controller) is designed with logic to control a protocol that functions with a variety of response latencies. With the additional logic, the devices do not need to be changed when pipeline stages are inserted in the various paths. Registers are utilized as the pipeline stages that are inserted within the paths.
摘要翻译： 一种设计芯片上的系统（SoC）以在不同的延迟和频率下工作的方法。 芯片的布局设计具有特定的器件布局，包括总线控制器，启动器和目标器件。 相对于默认传播时间确定信号从源设备传播到目的地设备的时间。 然后，在信号需要传播的每个附加时间，将流水线级插入到所述源设备和目的设备之间的总线路径中。 每个设备（即，启动器，目标和总线控制器）被设计为具有控制以各种响应延迟起作用的协议的逻辑。 使用附加逻辑，当管道级插入各种路径时，不需要更改设备。 寄存器被用作插入到路径内的流水线级。
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7.发明授权公开(公告)号：US06826656B2
公开(公告)日：2004-11-30
申请号：US10059537
申请日：2002-01-28
申请人： Victor Roberts Augsburg , James Norris Dieffenderfer , Bernard Charles Drerup , Richard Gerard Hofmann , Thomas Andrew Sartorius , Barry Joe Wolford
发明人： Victor Roberts Augsburg , James Norris Dieffenderfer , Bernard Charles Drerup , Richard Gerard Hofmann , Thomas Andrew Sartorius , Barry Joe Wolford
IPC分类号： G06F1208
CPC分类号： G06F1/3203 , G06F1/3275 , G06F12/0831 , Y02D10/14
摘要： A method and system for reducing power in a snooping cache based environment. A memory may be coupled to a plurality of processing units via a bus. Each processing unit may comprise a cache controller coupled to a cache associated with the processing unit. The cache controller may comprise a segment register comprising N bits where each bit in the segment register may be associated with a segment of memory divided into N segments. The cache controller may be configured to snoop a requested address on the bus. Upon determining which bit in the segment register is associated with the snooped requested address, the segment register may determine if the bit associated with the snooped requested address is set. If the bit is not set, then a cache search may not be performed thereby mitigating the power consumption associated with a snooped request cache search.
摘要翻译： 一种用于在基于窥探缓存的环境中降低功耗的方法和系统。 存储器可以经由总线耦合到多个处理单元。 每个处理单元可以包括耦合到与处理单元相关联的高速缓存器的高速缓存控制器。 高速缓存控制器可以包括包括N个比特的分段寄存器，其中分段寄存器中的每个比特可以与划分成N个分段的一段存储器相关联。 高速缓存控制器可以被配置为窥探总线上的所请求的地址。 一旦确定段寄存器中的哪个位与被窥探的请求地址相关联，则段寄存器可以确定是否设置与被窥探的请求地址相关联的位。 如果该位未设置，则可能不执行高速缓存搜索，从而减轻与窥探请求高速缓存搜索相关联的功耗。
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8.发明授权公开(公告)号：US07174410B2
公开(公告)日：2007-02-06
申请号：US10418593
申请日：2003-04-17
CPC分类号： G06F13/4027
摘要： A first device is operable to communicate on an bus according to a first protocol. A bridge is also operable to communicate on the bus according to the first protocol. A second device is coupled to the bus via the bridge and operable to communicate according to a second protocol. The bridge has a memory for holding data received from the second device and is operable to translate from the second to the first protocol. The second device sends write data responsive to receiving a ready signal from the bridge, and includes memory for holding the write data that the second device has sent, but for which completion has not been signaled. The second device re-sends the write data from the memory responsive to receiving a non-completion signal via the bridge, and releases the memory for the data responsive to receiving a completion signal via the bridge.
摘要翻译： 第一设备可操作以根据第一协议在总线上进行通信。 桥接器还可操作以根据第一协议在总线上进行通信。 第二设备经由桥耦合到总线并且可操作以根据第二协议进行通信。 桥具有用于保存从第二设备接收的数据的存储器，并且可操作以从第二协议转换为第一协议。 第二设备响应于从桥接收准备信号而发送写数据，并且包括用于保存第二设备已经发送的写入数据的存储器，但是还没有发出完成信号。 响应于经由桥接器接收到非完成信号，第二设备从存储器重新发送写入数据，并且响应于经由桥接器接收完成信号而释放用于数据的存储器。
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9.发明授权Re-ordering a first request within a FIFO request queue to a different queue position when the first request receives a retry response from the target 失效当第一个请求从目标接收到重试响应时，将FIFO请求队列内的第一请求重新排序到不同的队列位置公开(公告)号：US07035958B2
公开(公告)日：2006-04-25
申请号：US10264170
申请日：2002-10-03
申请人： Victor Roberts Augsburg , James Norris Dieffenderfer , Bernard Charles Drerup , Richard Gerard Hofmann , Thomas Andrew Sartorius , Barry Joe Wolford
发明人： Victor Roberts Augsburg , James Norris Dieffenderfer , Bernard Charles Drerup , Richard Gerard Hofmann , Thomas Andrew Sartorius , Barry Joe Wolford
IPC分类号： G06F13/36
CPC分类号： G06F13/362 , G06F13/4022 , G06F2213/0038
摘要： A method of operating a request FIFO of a system on a chip (SoC) in which a requests in a first position that has been granted and which subsequently receives a retry from the intended target is automatically re-ordered with respect to the other requests below it in the request FIFO. Each issued requests is tagged to either enable or disable a re-order feature. When a request that is tagged as re-order enabled is granted, the FIFO logic monitors the response provided for the request. If the response is a retry, the request is removed from the first position of the request FIFO and the next sequential request is moved into the first position. The removed requests may be re-ordered within the request FIFO or sent back to the initiator. In the former implementation, controller logic reorders the first request within the request FIFO. In the latter implementation, the controller logic of the bus controller messages the initiator when a request has been retried and subsequently removed from the first position of the request FIFO. The initiator then determines whether or not to re-issue the request.
摘要翻译： 一种操作芯片上系统（SoC）的请求FIFO的方法，其中已经被许可的第一个位置的请求和随后从预期目标接收到重试的请求自动地按照下面的其他请求重新排序 它在请求FIFO中。 每个发出的请求被标记为启用或禁用重新排序功能。 当被标记为启用重新排序的请求被授予时，FIFO逻辑监视为请求提供的响应。 如果响应是重试，则请求从请求FIFO的第一位置移除，并且下一个顺序请求被移动到第一位置。 删除的请求可以在请求FIFO内重新排序或发送回发起者。 在前面的实现中，控制器逻辑重新排序请求FIFO中的第一个请求。 在后一实现中，总线控制器的控制器逻辑在请求已被重试并随后从请求FIFO的第一位置移除时消息发起者。 然后，启动器确定是否重新发出请求。
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公开(公告)号：US06907502B2
公开(公告)日：2005-06-14
申请号：US10264169
申请日：2002-10-03
申请人： Victor Roberts Augsburg , James Norris Dieffenderfer , Bernard Charles Drerup , Jaya Prakash Subramaniam Ganasan , Richard Gerard Hofmann , Thomas Andrew Sartorius , Thomas Philip Speier , Barry Joe Wolford
发明人： Victor Roberts Augsburg , James Norris Dieffenderfer , Bernard Charles Drerup , Jaya Prakash Subramaniam Ganasan , Richard Gerard Hofmann , Thomas Andrew Sartorius , Thomas Philip Speier , Barry Joe Wolford
CPC分类号： G06F12/0831
摘要： A method for prioritizing snoop pushes in a data processing system that schedules requests within a request FIFO. Each new request that is received is placed in the last position of the request FIFO and the request FIFO typically grants request based solely on the order within the request FIFO. As prior requests are sequentially granted the subsequent requests move closer to a first position of the request FIFO. However, when a snoop push is received at the request FIFO, the snoop push is automatically inserted at the first position of the request FIFO ahead of all yet to be granted requests within the request FIFO.
摘要翻译： 一种用于将窥探优先级的方法推送到在请求FIFO内调度请求的数据处理系统中。 接收到的每个新请求被置于请求FIFO的最后位置，并且请求FIFO通常仅基于请求FIFO内的顺序授予请求。 由于先前请求被顺序授权，所以随后的请求更接近请求FIFO的第一位置。 然而，当在请求FIFO处接收到窥探推送时，窥探推送将自动插入请求FIFO的第一个位置，而在请求FIFO之前尚未被授予请求。
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