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47 条记录 (耗时 0.03 秒)

    Optical navigation sensor with integrated lens
    42.
    发明授权
    Optical navigation sensor with integrated lens 有权
    带集成镜头的光学导航传感器

    公开(公告)号：US07045775B2

    公开(公告)日：2006-05-16

    申请号：US11182226

    申请日：2005-07-15

    申请人： Ak Wing Leong ,  Gurbir Singh ,  Poh Huat Lye ,  Sai Mun Lee

    发明人： Ak Wing Leong ,  Gurbir Singh ,  Poh Huat Lye ,  Sai Mun Lee

    IPC分类号： H01J40/14

    CPC分类号： G06F3/0317

    摘要： An optical navigation sensor apparatus for an optical mouse includes an optical navigation sensor having an electronic chip, an aperture plate and an imaging lens integrated into a single package. The imaging lens includes a lens housing surrounding the aperture and providing a barrier to the entry of foreign matter into the aperture. In one form, the optical navigation sensor also includes a light emitting diode (LED) for illuminating a small area of a surface under the sensor and generating a reflected image that is detected by the electronic chip. In a sensor having an integral LED, an integral collimating lens is included for receiving light from the LED and focusing the light from the LED on the surface to be illuminated. The collimating lens is incorporated into a lens housing surrounding the LED and protecting the LED from exposure to foreign material.

    摘要翻译： 一种用于光学鼠标的光学导航传感器装置包括具有集成到单个封装中的电子芯片，孔板和成像透镜的光学导航传感器。 成像透镜包括围绕孔的透镜壳体，并且提供了将异物进入孔的障碍物。 在一种形式中，光学导航传感器还包括发光二极管（LED），用于照亮传感器下方的表面的小区域，并产生由电子芯片检测的反射图像。 在具有整体LED的传感器中，包括用于接收来自LED的光并且将来自LED的光聚焦在待照亮的表面上的整体准直透镜。 准直透镜被结合到围绕LED的透镜壳体中并且防止LED暴露于异物。

    Quad pumped bus architecture and protocol
    43.
    发明授权
    Quad pumped bus architecture and protocol 有权

    公开(公告)号：US06609171B1

    公开(公告)日：2003-08-19

    申请号：US09474058

    申请日：1999-12-29

    申请人： Gurbir Singh ,  Robert J. Greiner ,  Stephen S. Pawlowski ,  David L. Hill ,  Donald D. Parker

    发明人： Gurbir Singh ,  Robert J. Greiner ,  Stephen S. Pawlowski ,  David L. Hill ,  Donald D. Parker

    IPC分类号： G06F112

    CPC分类号： G06F13/4217

    摘要： A bidirectional multidrop processor bus is connected to a plurality of bus agents. Bus throughput can be increased by operating the bus in a multi pumped signaling mode in which multiple information elements are driven onto a bus by a driving agent at a rate that is a multiple of the frequency of the bus clock. The driving agent also activates a strobe to identify sampling points for the information elements. Information elements for a request can be driven, for example, using a double pumped signaling mode in which two information elements are driven during one bus clock cycle. Data elements for a data line transfer can be driven, for example, using a quad pumped signaling mode in which four data elements are driven during one bus clock cycle. Multiple strobe signals can be temporarily activated in an offset or staggered arrangement to reduce the frequency of the strobe signals. Sampling symmetry can be improved by using only one type of edge (e.g., either the rising edges or the falling edges) of the strobe signals to identify the sampling points.

    Changing clock frequency
    44.
    发明授权
    Changing clock frequency 有权
    改变时钟频率

    公开(公告)号：US6118306A

    公开(公告)日：2000-09-12

    申请号：US302931

    申请日：1999-04-30

    申请人： John T. Orton ,  Cau L. Nguyen ,  Gurbir Singh ,  Xia Dai ,  Raviprakash Nagaraj ,  Edwin J. Pole, II

    发明人： John T. Orton ,  Cau L. Nguyen ,  Gurbir Singh ,  Xia Dai ,  Raviprakash Nagaraj ,  Edwin J. Pole, II

    IPC分类号： G01R31/30 ,  G01R23/02

    CPC分类号： G06F1/324 ,  G01R31/3016 ,  G06F1/3296 ,  Y02B60/1217 ,  Y02B60/1285

    摘要： A system includes a component (e.g., a processor) that includes a clock generator that generates an internal clock running at a frequency. A controller generates a clock frequency change indication and places the component into a low activity state (e.g., deep sleep, stop grant, or other state). The clock generator is reset by the clock frequency change indication to change the clock's frequency while the component is in the low activity state. Storage elements containing different values are selectable to set the clock frequency. The storage elements include fuse banks and input pins.

    摘要翻译： 一种系统包括一个组件（例如处理器），该组件包括产生以一个频率运行的内部时钟的时钟发生器。 控制器产生时钟频率变化指示并将组件置于低活动状态（例如，深度睡眠，停止授权或其他状态）。 时钟发生器由时钟频率变化指示复位，以在组件处于低活动状态时更改时钟频率。 可以选择包含不同值的存储元件来设置时钟频率。 存储元件包括熔丝组和输入引脚。

    Microprocessor simultaneously issues an access to an external cache over an external cache bus and to an internal cache, cancels the external cache access on an internal cache hit, and reissues the access over a main memory bus on an external cache miss
    47.
    发明授权
    Microprocessor simultaneously issues an access to an external cache over an external cache bus and to an internal cache, cancels the external cache access on an internal cache hit, and reissues the access over a main memory bus on an external cache miss 失效
    微处理器同时通过外部高速缓存总线和内部高速缓存访​​问外部缓存，取消内部高速缓存命中的外部高速缓存访​​问，并通过外部缓存未命中的主存储器总线重新发出访问

    公开(公告)号：US5345576A

    公开(公告)日：1994-09-06

    申请号：US816603

    申请日：1991-12-31

    申请人： Phillip G. Lee ,  Eileen Riggs ,  Gurbir Singh ,  Randy Steck

    发明人： Phillip G. Lee ,  Eileen Riggs ,  Gurbir Singh ,  Randy Steck

    IPC分类号： G06F12/08 ,  G06F13/00

    CPC分类号： G06F12/0884 ,  G06F12/0897

    摘要： A data processing system which includes a microprocessor fabricated on an integrated circuit chip, a main memory external to the integrated circuit chip, and a backside cache external to the integrated circuit chip. The backside cache includes a directory RAM for storing cache address tag and encoded cache state bits. A first bus connects the microprocessor to the cache, the first bus including backside bus cache directory tags signals comprised of address bits used for a cache hit comparison in the directory RAM and backside bus cache directory state bits for determining a state encoding of a set in the directory RAM. A second bus connects the microprocessor to the main memory. The directory includes means for comparing the cache directory tags on the first bus with the tags stored in the directory and for asserting a Bmiss signal upon the condition that the directory tag stored in the backside bus cache directory do not match the backside bus cache directory tags signals. The microprocessor responds to the Bmiss signal by issuing the access onto the second bus in the event of a cache miss.

    摘要翻译： 一种数据处理系统，包括在集成电路芯片上制造的微处理器，集成电路芯片外部的主存储器和集成电路芯片外部的背面高速缓存器。 背面缓存包括用于存储高速缓存地址标签和编码高速缓存状态位的目录RAM。 第一总线将微处理器连接到高速缓存，第一总线包括背面总线缓存目录标签信号，其包括用于目录RAM中的高速缓存命中比较的地址位和用于确定目标RAM中的集合的状态编码的背面总线缓存目录状态位 目录RAM。 第二个总线将微处理器连接到主存储器。 该目录包括用于将第一总线上的高速缓存目录标签与存储在目录中的标签进行比较并用于在存储在背面总线缓存目录中的目录标签与背面总线缓存目录标签不匹配的情况下断言Bmiss信号的装置 信号。 在缓存未命中的情况下，微处理器通过发出对第二总线的访问来响应Bmiss信号。