公开(公告)号：US06532185B2

公开(公告)日：2003-03-11

申请号：US09792605

申请日：2001-02-23

申请人： Jean Louis Calvignac ,  Peter Irma August Barri ,  Ivan Oscar Clemminck ,  Kent Harold Haselhorst ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Bart Joseph Gerard Pauwels ,  Fabrice Jean Verplanken ,  Miroslav Vrana

发明人： Jean Louis Calvignac ,  Peter Irma August Barri ,  Ivan Oscar Clemminck ,  Kent Harold Haselhorst ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Bart Joseph Gerard Pauwels ,  Fabrice Jean Verplanken ,  Miroslav Vrana

IPC分类号： G11C800

CPC分类号： H04L49/901 ,  G06F12/0607 ,  H04L49/90 ,  H04L49/9031

摘要： Network processors commonly utilize DRAM chips for the storage of data. Each DRAM chip contains multiple banks for quick storage of data and access to that data. Latency in the transfer or the ‘write’ of data into memory can occur because of a phenomenon referred to as memory bank polarization. By a procedure called quadword rotation, this latency effect is effectively eliminated. Data frames received by the network processor are transferred to a receive queue (FIFO). The frames are divided into segments that are written into the memory of the DRAM in accordance with a formula that rotates the distribution of each segment into the memory banks of the DRAM.

公开(公告)号：US07627701B2

公开(公告)日：2009-12-01

申请号：US12120419

申请日：2008-05-14

申请人： Claude Basso ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

发明人： Claude Basso ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

IPC分类号： G06F5/00 ,  G06F15/16

CPC分类号： H04L49/901 ,  H04L49/103 ,  H04L49/3018 ,  H04L49/90 ,  H04L49/9094

摘要： A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes several control blocks, one for each data buffer, each containing control information linking one buffer to another. Each control block has a last bit feature which is a single bit settable to “one or “zero” and indicates the transmission of when the data buffer having the last bit. The last bit is in a first position when an additional data buffer is to be chained to a previous data buffer indicating an additional data buffer is to be transmitted and a second position when no additional data buffer is to be chained to a previous data buffer. The position of the last bit is communicated to the network processor indicating the ending of a particular frame.

摘要翻译： 提供了一种用于确定在网络处理器中正在发送的一个或多个数据缓冲器组成的信息帧何时完成传输的方法和结构。 网络处理器包括几个控制块，每个数据缓冲器一个，每个包含将一个缓冲器链接到另一个的控制信息。 每个控制块具有最后一位特征，其是可设置为“一个或”零“的单个位，并且指示何时数据缓冲器具有最后位，当最后一位处于第一位置时，当附加数据缓冲器为 被链接到先前的数据缓冲器，指示要发送附加数据缓冲器，并且当没有附加数据缓冲器被链接到先前的数据缓冲器时的第二位置，最后位的位置被传送到指示结束的网络处理器 的特定框架。

公开(公告)号：US07506081B2

公开(公告)日：2009-03-17

申请号：US10850219

申请日：2004-05-20

申请人： Peter Irma August Barri ,  Jean Louis Calvignac ,  Kent Harold Haselhorst ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken ,  Miroslav Vrana

发明人： Peter Irma August Barri ,  Jean Louis Calvignac ,  Kent Harold Haselhorst ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken ,  Miroslav Vrana

IPC分类号： G06F3/00

CPC分类号： G11C7/1066 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/1078 ,  G11C11/4093

摘要： A Network Processor includes a Fat Pipe Port and a memory sub-system that provides sufficient data to satisfy the Bandwidth requirements of the Fat Pipe Port. The memory sub-system includes a plurality of DDR DRAMs controlled so that data is extracted from one DDR DRAM or simultaneously from a plurality of the DDR DRAMs. By controlling the DDR DRAMs so that the outputs provide data serially or in parallel, the data Bandwidth is adjustable over a wide range. Similarly, data is written serially into one DDR DRAM or simultaneously into multiple DDR DRAMs. As a consequence buffers with data from the same frame are written into or read from different DDR DRAMs.

摘要翻译： 网络处理器包括胖管端口和存储器子系统，其提供足够的数据以满足胖管端口的带宽要求。 存储器子系统包括被控制的多个DDR DRAM，从而从一个DDR DRAM提取数据或者同时从多个DDR DRAM中提取数据。 通过控制DDR DRAM，使得输出串行或并行提供数据，数据带宽可在宽范围内调节。 类似地，数据被串行地写入一个DDR DRAM或同时被写入多个DDR DRAM。 因此，来自相同帧的数据的缓冲器被写入或从不同的DDR DRAM中读取。

公开(公告)号：US07130916B2

公开(公告)日：2006-10-31

申请号：US09791336

申请日：2001-02-23

申请人： Jean Louis Calvignac ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

发明人： Jean Louis Calvignac ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

IPC分类号： G06F15/167 ,  G06F12/00 ,  G06F12/16 ,  G06F13/28 ,  G06F9/44 ,  H04L12/54 ,  G06F15/16 ,  G06F12/14 ,  G06F13/00 ,  G06F3/00 ,  G06F9/46

CPC分类号： H04L49/3081 ,  G06F13/4243 ,  H04L2012/5681

摘要： A method and system for reducing memory accesses by inserting qualifiers in control blocks. In one embodiment, a system comprises a processor configured to process frames of data. The processor may comprise a plurality of buffers configured to store frames of data where each frame of data may be associated with a frame control block. Each frame control block associated with a frame of data may be associated with one or more buffer control blocks. Each control block, e.g., frame control block, buffer control block, may comprise one or more qualifier fields that comprise information unrelated to the current control block. Instead, qualifiers may comprise information related to an another control block. The last frame control block in a queue as well as the last buffer control block associated with a frame control block may comprise fields with no information thereby reducing memory accesses to access information in those fields.

公开(公告)号：US06836480B2

公开(公告)日：2004-12-28

申请号：US09839079

申请日：2001-04-20

申请人： Claude Basso ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

发明人： Claude Basso ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

IPC分类号： H04L1256

CPC分类号： H04L49/901 ,  H04L12/1881 ,  H04L47/10 ,  H04L47/20 ,  H04L49/90

摘要： Data structures, a method, and an associated transmission system for multicast transmission on network processors in order both to minimize multicast transmission memory requirements and to account for port performance discrepancies. Frame data for multicast transmission on a network processor is read into buffers to which are associated various control structures and a reference frame. The reference frame and the associated control structures permit multicast targets to be serviced without creating multiple copies of the frame. Furthermore this same reference frame and control structures allow buffers allocated for each multicast target to be returned to the free buffer queue without waiting until all multicast transmissions are complete.

摘要翻译： 数据结构，方法和相关的传输系统，用于网络处理器上的组播传输，以便最大限度地减少组播传输内存的需求并解决端口性能差异。 将网络处理器上的组播传输的帧数据读入与各种控制结构和参考帧相关联的缓冲器。 参考帧和相关联的控制结构允许在不创建帧的多个拷贝的情况下对多播目标进行服务。 此外，相同的参考帧和控制结构允许为每个多播目标分配的缓冲区返回到空闲缓冲器队列，而不等待所有多播传输完成。

公开(公告)号：US20080215772A1

公开(公告)日：2008-09-04

申请号：US12100739

申请日：2008-04-10

申请人： Claude Basso ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

发明人： Claude Basso ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

IPC分类号： G06F5/00

CPC分类号： H04L49/901 ,  H04L49/103 ,  H04L49/3018 ,  H04L49/90 ,  H04L49/9094

摘要： A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes several control blocks, one for each data buffer, each containing control information linking one buffer to another. Each control block has a last bit feature which is a single bit settable to “one” or “zero” and indicates when the data buffer having the last bit is transmitted. The last bit is in a first position when an additional data buffer is to be chained to a previous data buffer indicating an additional data buffer is to be transmitted and a second position when no additional data buffer is to be chained to a previous data buffer. The position of the last bit is communicated to the network processor indicating the ending of a particular frame.

摘要翻译： 提供了一种用于确定在网络处理器中正在发送的一个或多个数据缓冲器组成的信息帧何时完成传输的方法和结构。 网络处理器包括几个控制块，每个数据缓冲器一个，每个包含将一个缓冲器链接到另一个的控制信息。 每个控制块具有最后一位特征，其是可设置为“一”或“零”的单个位，并且指示何时发送具有最后位的数据缓冲器。 当附加数据缓冲器被链接到先前的数据缓冲器，指示要发送附加数据缓冲器时，最后一位处于第一位置，而当没有附加数据缓冲器被链接到先前数据缓冲器时，最后一位处于第一位置。 最后一位的位置被传送到指示特定帧的结束的网络处理器。

公开(公告)号：US07412546B2

公开(公告)日：2008-08-12

申请号：US11320277

申请日：2005-12-27

申请人： Claude Basso ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

发明人： Claude Basso ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

IPC分类号： G06F5/00 ,  G06F15/16

CPC分类号： H04L49/901 ,  H04L49/103 ,  H04L49/3018 ,  H04L49/90 ,  H04L49/9094

摘要： A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes several control blocks, one for each data buffer, each containing control information linking one buffer to another. Each control block has a last bit feature which is a single bit settable to “one or “zero” and indicates the transmission of when the data buffer having the last bit. The last bit is in a first position when an additional data buffer is to be chained to a previous data buffer indicating an additional data buffer is to be transmitted and a second position when no additional data buffer is to be chained to a previous data buffer. The position of the last bit is communicated to the network processor indicating the ending of a particular frame.

摘要翻译： 提供了一种用于确定在网络处理器中正在发送的一个或多个数据缓冲器组成的信息帧何时完成传输的方法和结构。 网络处理器包括几个控制块，每个数据缓冲器一个，每个包含将一个缓冲器链接到另一个的控制信息。 每个控制块具有最后一位特征，其是可设置为“一个或”零“的单个位，并且指示何时数据缓冲器具有最后位，当最后一位处于第一位置时，当附加数据缓冲器为 被链接到先前的数据缓冲器，指示要发送附加数据缓冲器，并且当没有附加数据缓冲器被链接到先前的数据缓冲器时的第二位置，最后位的位置被传送到指示结束的网络处理器 的特定框架。

公开(公告)号：US07200696B2

公开(公告)日：2007-04-03

申请号：US09828342

申请日：2001-04-06

申请人： Claude Basso ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

发明人： Claude Basso ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

IPC分类号： G06F15/16

CPC分类号： H04L49/901 ,  H04L49/103 ,  H04L49/3018 ,  H04L49/90 ,  H04L49/9094

摘要： A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes a plurality of control blocks, one for each data buffer, each containing control information to link one buffer to another for transmission. Each of the control blocks has a last bit feature which is a single bit and indicates when the data buffer having the last bit is transmitted. This last bit feature is a bit which can be set to either zero or one. The last bit feature is in a first position when an additional data buffer is to be chained to a previous data buffer indicating an additional data buffer is to be transmitted and a second position when no additional data buffer is to be chained to a previous data buffer. The position of the last bit feature is communicated to the network processor to indicate whether the transmission of a particular frame is ended and a new frame is to be transmitted.

摘要翻译： 提供了一种用于确定在网络处理器中正在发送的一个或多个数据缓冲器组成的信息帧何时完成传输的方法和结构。 网络处理器包括多个控制块，一个用于每个数据缓冲器，每个控制块包含用于将一个缓冲器链接到另一缓冲器以进行传输的控制信息。 每个控制块具有作为单个位的最后位特征，并且指示何时发送具有最后位的数据缓冲器。 这最后一位功能是一个可以设置为零或一个的位。 当附加数据缓冲器被链接到先前的数据缓冲器指示要发送附加数据缓冲器时，最后一位特征处于第一位置，而当没有附加数据缓冲器被链接到先前的数据缓冲器时，第二位置 。 将最后一位特征的位置传送给网络处理器，以指示特定帧的传输是否结束，并且要发送新的帧。

公开(公告)号：US06987760B2

公开(公告)日：2006-01-17

申请号：US09838395

申请日：2001-04-19

申请人： Jean Louis Calvignac ,  William John Goetzinger ,  Glen Howard Handlogten ,  Marco C. Heddes ,  Joseph Franklin Logan ,  James Francis Mikos ,  David Alan Norgaard ,  Fabrice Jean Verplanken

发明人： Jean Louis Calvignac ,  William John Goetzinger ,  Glen Howard Handlogten ,  Marco C. Heddes ,  Joseph Franklin Logan ,  James Francis Mikos ,  David Alan Norgaard ,  Fabrice Jean Verplanken

IPC分类号： H04L12/56

CPC分类号： H04L12/5601 ,  H04L2012/5636 ,  H04L2012/5679 ,  H04L2012/5685

摘要： A Network Processor (NP) is formed from a plurality of operatively coupled chips. The NP includes a Network Processor Complex (NPC) Chip coupled to a Data Flow Chip and Data Store Memory coupled to the Data Flow Chip. An optional Scheduler Chip is coupled to the Data Flow Chip. The named components are replicated to create a symmetric ingress and egress structure.

公开(公告)号：US06681340B2

公开(公告)日：2004-01-20

申请号：US09792533

申请日：2001-02-23

申请人： Jean Louis Calvignac ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

发明人： Jean Louis Calvignac ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

IPC分类号： G06F1110

CPC分类号： H04L1/0043 ,  H04L1/0063

摘要： A method and system for efficiently implementing an error correction code scheme. In one embodiment of the present invention, a system comprises a processor configured to process frames of data. Each frame of data may be associated with a frame control block. The processor comprises a first queue configured to store one or more frame control blocks associated with one or more frames of data. The processor further comprises a second queue configured to store one or more frame control blocks not associated with a frame of data. The one or more frame control blocks associated with one or more frames of data in the first queue comprise a bit for storing a parity bit. The one or more frame control blocks in the second queue comprise a plurality of bits for storing a code of an error correction code scheme.

摘要翻译： 一种用于有效实施纠错码方案的方法和系统。 在本发明的一个实施例中，系统包括被配置为处理数据帧的处理器。 数据帧可以与帧控制块相关联。 处理器包括被配置为存储与一个或多个数据帧相关联的一个或多个帧控制块的第一队列。 处理器还包括被配置为存储与数据帧不相关联的一个或多个帧控制块的第二队列。 与第一队列中的一个或多个数据帧相关联的一个或多个帧控制块包括用于存储奇偶校验位的位。 第二队列中的一个或多个帧控制块包括用于存储纠错码方案的代码的多个比特。