Method and System for Frequency Conversion for Bluetooth and FM
    41.
    发明申请
    Method and System for Frequency Conversion for Bluetooth and FM 审中-公开
    蓝牙和FM频率转换方法和系统

    公开(公告)号:US20070298833A1

    公开(公告)日:2007-12-27

    申请号:US11425551

    申请日:2006-06-21

    IPC分类号: H04B7/00 H04B1/40

    CPC分类号: H04B1/034 H04B1/207

    摘要: Methods and systems frequency conversion for Bluetooth and FM radio are provided. FM data may be received and/or transmitted via the FM radio and Bluetooth data may be received and/or transmitted via the Bluetooth radio. With an integration of frequency conversion for Bluetooth and FM, both systems may operate from a single frequency source, thereby reducing part count and power consumption. Communication between Bluetooth and FM channels may be enabled via a single chip.

    摘要翻译: 提供蓝牙和FM收音机的方法和系统变频。 可以通过FM收音机接收和/或发送FM数据,并且可以经由蓝牙无线电接收和/或发送蓝牙数据。 通过集成蓝牙和FM的频率转换,两个系统都可以从单个频率源进行操作,从而减少部件数量和功耗。 蓝牙和FM频道之间的通信可以通过单个芯片启用。

    Electronic system having a chip integrated power-on reset circuit with
glitch sensor
    43.
    发明授权
    Electronic system having a chip integrated power-on reset circuit with glitch sensor 失效
    电子系统具有带有毛刺传感器的芯片集成上电复位电路

    公开(公告)号:US6085342A

    公开(公告)日:2000-07-04

    申请号:US851875

    申请日:1997-05-06

    CPC分类号: G06F11/1441

    摘要: A power-on reset circuit with glitch sensing capabilities is formed as part of the same integrated circuit chip containing other logical circuits. A port included in the integrated circuit chip enables a power-on reset signal generated by the integrated power-on reset circuit to be output from the chip and applied to other chips installed in a single chip or multi-chip electronic system. The power-on reset circuit compares a capacitor stored reset voltage to a reference voltage and outputs the power-on reset signal when the reset voltage falls below the reference voltage. Storage of the reset voltage by the capacitor is controlled by a glitch sensor which detects changes in voltage provided by a power supply in excess of a given threshold and, in response thereto, triggers a capacitor discharge. This causes the reset voltage to fall below the reference voltage, and the power-on reset signal to be output. Furthermore, for synchronously operated systems, the output power-on reset signal is synchronized with an edge of an output clock signal.

    摘要翻译: 具有毛刺检测能力的上电复位电路被形成为包含其他逻辑电路的相同集成电路芯片的一部分。 集成电路芯片中包括的端口使得能够从集成电源复位电路产生的上电复位信号从芯片输出并施加到安装在单芯片或多芯片电子系统中的其他芯片。 上电复位电路将电容器存储的复位电压与参考电压进行比较,并在复位电压低于参考电压时输出上电复位信号。 通过电容器的复位电压的存储由检测由电源提供的电压的变化超过给定阈值的毛刺传感器控制,并且响应于此触发电容器放电。 这将导致复位电压低于参考电压,并且上电复位信号被输出。 此外,对于同步操作的系统,输出上电复位信号与输出时钟信号的边沿同步。

    Method and system for single chip WLAN and bluetooth radios on a single CMOS substrate
    45.
    发明授权
    Method and system for single chip WLAN and bluetooth radios on a single CMOS substrate 有权
    在单个CMOS基板上单芯片WLAN和蓝牙无线电的方法和系统

    公开(公告)号:US08600300B2

    公开(公告)日:2013-12-03

    申请号:US11618869

    申请日:2006-12-31

    IPC分类号: H04B5/00

    CPC分类号: H04B1/406 H04W88/00

    摘要: Aspects of a method and system for single chip WLAN and Bluetooth radios on a single CMOS substrate are presented. Aspects of the system may include a WLAN receiver circuit within a substrate of a single chip that enables reception of WLAN signals, and a Bluetooth receiver circuit within the same substrate that enables reception of Bluetooth signals. The WLAN receiver circuit and Bluetooth receiver circuit may utilize a single low noise amplifier circuit that enables reception of the WLAN signals and Bluetooth signals. Aspects of the system may also include a WLAN transmitter circuit within a substrate of a single chip that enables transmission of WLAN signals, and a Bluetooth transmitter circuit within the same substrate that enables transmission of Bluetooth signals. The WLAN transmitter circuit and Bluetooth transmitter circuit may utilize a single power amplifier circuit that enables transmission of the WLAN signals and Bluetooth signals.

    摘要翻译: 提出了单个CMOS基板上的单芯片WLAN和蓝牙无线电的方法和系统的方面。 该系统的方面可以包括能够接收WLAN信号的单个芯片的基板内的WLAN接收器电路,以及能够接收蓝牙信号的同一基板内的蓝牙接收器电路。 WLAN接收器电路和蓝牙接收器电路可以使用能够接收WLAN信号和蓝牙信号的单个低噪声放大器电路。 该系统的方面还可以包括能够传输WLAN信号的单个芯片的基板内的WLAN发射机电路,以及能够传输蓝牙信号的同一基板内的蓝牙发射机电路。 WLAN发射机电路和蓝牙发射机电路可以利用能够传输WLAN信号和蓝牙信号的单个功率放大器电路。

    METHOD AND SYSTEM FOR SHARING FILTERS BETWEEN TRANSMIT AND RECEIVE PATHS IN AN INTEGRATED FM RADIO
    47.
    发明申请
    METHOD AND SYSTEM FOR SHARING FILTERS BETWEEN TRANSMIT AND RECEIVE PATHS IN AN INTEGRATED FM RADIO 审中-公开
    在一体化FM无线电中发送和接收数据之间共享过滤器的方法和系统

    公开(公告)号:US20080232279A1

    公开(公告)日:2008-09-25

    申请号:US11938007

    申请日:2007-11-09

    申请人: Bojko Marholev

    发明人: Bojko Marholev

    IPC分类号: H04B1/40 H04J3/00

    CPC分类号: H04B1/403

    摘要: Aspects of a method and system for sharing filters between transmit and receive paths in an integrated FM radio are provided. In this regard, a FM radio receive processing path and a FM radio transmit processing path may each be configured to share a filter. Accordingly, one or more switching elements may enable coupling/decoupling the filter to/from the FM radio transmit and FM radio receive processing paths. Furthermore, the switching elements may be programmatically controlled by a processor and/or memory. Additionally, by coupling the filter to the transmit receive paths during alternating time intervals, aspects of the invention may enable simulating simultaneous transmission and reception of FM radio signals utilizing while sharing one or more filters. In various embodiments of the invention, separate filters may be utilized for an in-phase processing path and a quadrature phase processing path.

    摘要翻译: 提供了一种用于在集成FM收音机中的发送和接收路径之间共享滤波器的方法和系统的方面。 在这方面,FM无线电接收处理路径和FM无线电发送处理路径可以各自被配置为共享过滤器。 因此,一个或多个开关元件可以使滤波器与FM无线电发射和FM无线电接收处理路径耦合/去耦合。 此外,开关元件可以由处理器和/或存储器编程地控制。 另外,通过在交替时间间隔期间将滤波器耦合到发射接收路径,本发明的各方面可以使得在共享一个或多个滤波器的同时模拟FM无线电信号的同时传输和接收。 在本发明的各种实施例中,分离的滤波器可以用于同相处理路径和正交相位处理路径。

    Method and System for Shared High-Power Transmit Path for a Multi-Protocol Transceiver
    48.
    发明申请
    Method and System for Shared High-Power Transmit Path for a Multi-Protocol Transceiver 审中-公开
    用于多协议收发器的共享大功率发射路径的方法和系统

    公开(公告)号:US20080137566A1

    公开(公告)日:2008-06-12

    申请号:US11618848

    申请日:2006-12-31

    IPC分类号: H04B7/00

    摘要: Aspects of a method and system for a shared high-power transmit path for a multi-protocol transceiver are disclosed. Aspects of one method may include sharing a first power amplifier with a WLAN signal and a Bluetooth signal. The first power amplifier may amplify the WLAN signal and/or the Bluetooth signal simultaneously, or individually. A second power amplifier may be used to amplify the Bluetooth signal, where the first power amplifier may have a higher gain than the second power amplifier. Power may be reduced to the second power amplifier in instances where the first power amplifier is used to amplify the Bluetooth signal. The Bluetooth signal may be communicated to the first power amplifier via a switching circuit, which may comprise one or more switching stages.

    摘要翻译: 公开了用于多协议收发器的共享高功率发射路径的方法和系统的方面。 一种方法的方面可以包括共享具有WLAN信号和蓝牙信号的第一功率放大器。 第一功率放大器可以同时或单独地放大WLAN信号和/或蓝牙信号。 可以使用第二功率放大器来放大蓝牙信号,其中第一功率放大器可以具有比第二功率放大器更高的增益。 在使用第一功率放大器来放大蓝牙信号的情况下,功率可以减小到第二功率放大器。 蓝牙信号可以经由开关电路传送到第一功率放大器,开关电路可以包括一个或多个开关级。

    Method and System for Buffering A Clock Signal
    49.
    发明申请
    Method and System for Buffering A Clock Signal 审中-公开
    缓冲时钟信号的方法和系统

    公开(公告)号:US20080136498A1

    公开(公告)日:2008-06-12

    申请号:US11618863

    申请日:2006-12-31

    IPC分类号: H03K3/01

    摘要: A method and system for buffering a clock signal is provided. The method may include self-biasing a PMOS transistor of a buffer, utilized for amplifying an in-phase/quadrature phase signal, to produce a first bias voltage at the gate of a PMOS transistor, and biasing an NMOS transistor of the buffer via a controllable current source to produce a second bias voltage at the gate of the NMOS transistor. The gain of the buffer may be controlled by varying a controllable current source coupled to a second NMOS transistor configured as a diode. Two coupling capacitors may be utilized to remove a DC component of the signal. Multiple buffers may be coupled end-to-end to increase the overall drive capability, where the channel width of the transistors within the transistors may be doubled in each successive buffer.

    摘要翻译: 提供了一种用于缓冲时钟信号的方法和系统。 该方法可以包括自偏压缓冲器的PMOS晶体管,用于放大同相/正交相位信号,以在PMOS晶体管的栅极处产生第一偏置电压,并经由一个PMOS晶体管偏置缓冲器的NMOS晶体管 可控电流源,以在NMOS晶体管的栅极处产生第二偏置电压。 可以通过改变耦合到配置为二极管的第二NMOS晶体管的可控电流源来控制缓冲器的增益。 可以使用两个耦合电容器来去除信号的DC分量。 多个缓冲器可以端对端耦合以增加总体驱动能力,其中晶体管内的晶体管的沟道宽度可以在每个连续的缓冲器中加倍。

    Supply independent Schmitt trigger RC oscillator
    50.
    发明申请
    Supply independent Schmitt trigger RC oscillator 有权
    供应独立的施密特触发器RC振荡器

    公开(公告)号:US20070069828A1

    公开(公告)日:2007-03-29

    申请号:US11236191

    申请日:2005-09-27

    IPC分类号: H03B5/20

    CPC分类号: H03K4/502

    摘要: Embodiments of the present invention provide an oscillator circuit having a steady output frequency that is independent of the supplied voltage. This oscillator includes a Schmitt trigger circuit which may be implemented within an integrated circuit of a wireless terminal or other like portable electronic device. The Schmitt trigger circuit receives a threshold voltage input and a second voltage input. The Schmitt trigger circuit generates an output voltage equal to either a first output voltage or a second output voltage based on the results of comparing the threshold voltage input to the second voltage input. An RC network may be coupled to the output of the Schmitt trigger circuit and is operable to supply the second voltage input to the Schmitt trigger circuit. A voltage divider network also couples to the output of the Schmitt trigger circuit wherein the threshold voltage input is proportional to the first output voltage reduced by the voltage divider network based on the output voltage of the Schmitt trigger circuit.

    摘要翻译: 本发明的实施例提供一种具有稳定的输出频率的振荡器电路,其独立于所提供的电压。 该振荡器包括可在无线终端或其它类似便携式电子设备的集成电路内实施的施密特触发电路。 施密特触发电路接收阈值电压输入和第二电压输入。 基于比较输入到第二电压输入的阈值电压的结果,施密特触发电路产生等于第一输出电压或第二输出电压的输出电压。 RC网络可以耦合到施密特触发电路的输出,并且可操作以将第二电压输入提供给施密特触发电路。 分压网络还耦合到施密特触发电路的输出,其中阈值电压输入与基于施密特触发电路的输出电压的分压器网络降低的第一输出电压成比例。