公开(公告)号：US20060124982A1

公开(公告)日：2006-06-15

申请号：US10905094

申请日：2004-12-15

申请人： Herbert Ho ,  John Barth ,  Ramachandra Divakaruni ,  Wayne Ellis ,  Johnathan Faltermeier ,  Brent Anderson ,  Subramanian Iyer ,  Deok-Kee Kim ,  Randy Mann ,  Paul Parries

发明人： Herbert Ho ,  John Barth ,  Ramachandra Divakaruni ,  Wayne Ellis ,  Johnathan Faltermeier ,  Brent Anderson ,  Subramanian Iyer ,  Deok-Kee Kim ,  Randy Mann ,  Paul Parries

IPC分类号： H01L29/94 ,  H01L27/108

CPC分类号： H01L27/0805 ,  H01L29/66181 ,  H01L29/945

摘要： A novel trench-type decoupling capacitor structure and low-cost manufacturing process to create trench decoupling capacitors (decaps). In a unique aspect, the invention necessitates the addition of only a simplified trench to a base logic design.

摘要翻译： 一种新颖的沟槽型去耦电容器结构和低成本制造工艺，以创建沟槽去耦电容器（decaps）。 在一个独特的方面，本发明仅需要在基本逻辑设计中添加简化的沟槽。

公开(公告)号：US08299570B2

公开(公告)日：2012-10-30

申请号：US13189016

申请日：2011-07-22

申请人： Deok-Kee Kim ,  Dureseti Chidambarrao ,  William K. Henson ,  Chandrasekharan Kothandaraman

发明人： Deok-Kee Kim ,  Dureseti Chidambarrao ,  William K. Henson ,  Chandrasekharan Kothandaraman

IPC分类号： H01L23/525

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： An eFuse, includes: a substrate and an insulating layer disposed on the substrate; a first layer including a single crystal or polycrystalline silicon disposed on the insulating layer; a second layer including a single crystal or polycrystalline silicon germanium disposed on the first layer, and a third layer including a silicide disposed on the second layer. The Ge has a final concentration in a range of approximately five percent to approximately twenty-five percent.

摘要翻译： eFuse包括：衬底和设置在衬底上的绝缘层; 包括设置在所述绝缘层上的单晶或多晶硅的第一层; 包括设置在第一层上的单晶或多晶硅锗的第二层，以及包括设置在第二层上的硅化物的第三层。 Ge的终浓度范围约为百分之五至百分之二十五。

公开(公告)号：US08013419B2

公开(公告)日：2011-09-06

申请号：US12136246

申请日：2008-06-10

申请人： Deok-Kee Kim ,  Ahmet S Ozcan ,  Haining S Yang

发明人： Deok-Kee Kim ,  Ahmet S Ozcan ,  Haining S Yang

IPC分类号： H01L23/52

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： An e-fuse structure and method has anode, a fuse link, and a cathode. The first end of the fuse link is connected to the anode and the second end of the fuse link opposite the first end is connected to the cathode. This structure also includes a first silicide layer on the anode and the fuse link and a second silicide layer, different than the first silicide layer, on the cathode. The difference between the first silicide layer and the second silicide layer causes an enhanced flux divergence region at the second end of the fuse link.

摘要翻译： 电熔丝结构和方法具有阳极，熔丝链和阴极。 熔丝链的第一端连接到阳极，并且与第一端相对的熔丝连接的第二端连接到阴极。 该结构还包括阴极上的阳极和熔丝链上的第一硅化物层和不同于第一硅化物层的第二硅化物层。 第一硅化物层和第二硅化物层之间的差异在熔丝链的第二端引起增强的磁通发散区域。

公开(公告)号：US07927968B2

公开(公告)日：2011-04-19

申请号：US12125106

申请日：2008-05-22

申请人： Deok-Kee Kim ,  Seong-Dong Kim ,  Oh-Jung Kwon

发明人： Deok-Kee Kim ,  Seong-Dong Kim ,  Oh-Jung Kwon

IPC分类号： H01L21/76

CPC分类号： H01L21/823807 ,  H01L21/823878 ,  H01L29/7846 ,  Y10S257/908

摘要： The embodiments of the invention provide a device, method, etc. for a dual stress STI. A semiconductor device is provided having a substrate with a first transistor region and a second transistor region different than the first transistor region. The first transistor region comprises a PFET; and, the second transistor region comprises an NFET. Further, STI regions are provided in the substrate adjacent sides of and positioned between the first transistor region and the second transistor region, wherein the STI regions each comprise a compressive region, a compressive liner, a tensile region, and a tensile liner.

摘要翻译： 本发明的实施例提供了用于双重应力STI的装置，方法等。 提供一种半导体器件，其具有具有与第一晶体管区域不同的第一晶体管区域和第二晶体管区域的衬底。 第一晶体管区域包括PFET; 并且第二晶体管区域包括NFET。 此外，STI区域设置在基板的相邻侧并位于第一晶体管区域和第二晶体管区域之间，其中STI区域各自包括压缩区域，压缩衬垫，拉伸区域和拉伸衬里。

公开(公告)号：US07838963B2

公开(公告)日：2010-11-23

申请号：US11925164

申请日：2007-10-26

申请人： Dureseti Chidambarrao ,  William K. Henson ,  Deok-Kee Kim ,  Chandrasekharan Kothandaraman

发明人： Dureseti Chidambarrao ,  William K. Henson ,  Deok-Kee Kim ,  Chandrasekharan Kothandaraman

IPC分类号： H01L29/86

CPC分类号： H01L23/5256 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

摘要： A contiguous block of a stack of two heterogeneous semiconductor layers is formed over an insulator region such as shallow trench isolation. A portion of the contiguous block is exposed to an etch, while another portion is masked during the etch. The etch removes an upper semiconductor layer selective to a lower semiconductor layer in the exposed portion. The etch mask is removed and the entirety of the lower semiconductor layer within the exposed region is metallized. A first metal semiconductor alloy vertically abutting the insulator region is formed, while exposed surfaces of the stack of two heterogeneous semiconductor layers, which comprises the materials of the upper semiconductor layer, are concurrently metallized to form a second metal semiconductor alloy. An inflection point for current and, consequently, a region of flux divergence are formed at the boundary of the two metal semiconductor alloys.

摘要翻译： 在绝缘体区域上形成两个不均匀半导体层的堆叠的连续块，例如浅沟槽隔离。 连续块的一部分暴露于蚀刻，而另一部分在蚀刻期间被掩蔽。 蚀刻去除在暴露部分中对下半导体层有选择性的上半导体层。 去除蚀刻掩模，并且暴露区域内的下半导体层的整体被金属化。 形成垂直邻接绝缘体区域的第一金属半导体合金，同时将包含上半导体层的材料的两个非均匀半导体层的堆叠的暴露表面同时金属化以形成第二金属半导体合金。 在两个金属半导体合金的边界处形成电流的拐点，从而形成磁通发散区域。

公开(公告)号：US07479689B2

公开(公告)日：2009-01-20

申请号：US11627384

申请日：2007-01-26

申请人： Deok-Kee Kim ,  Xiangdong Chen ,  Haining Yang

发明人： Deok-Kee Kim ,  Xiangdong Chen ,  Haining Yang

IPC分类号： H01L23/58

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electronically programmable fuse (e-fuse) is disclosed. In one embodiment, the e-fuse includes a cathode surrounded only by silicon dioxide; an anode; and a polysilicon-silicide programmable link coupling the anode and the cathode, wherein the anode and the polysilicon-silicide programmable link are surrounded by a low dielectric constant (low-k) material on a top and a side thereof.

摘要翻译： 公开了一种电子可编程保险丝（e-fuse）。 在一个实施例中，电熔丝包括仅被二氧化硅包围的阴极; 阳极; 以及耦合所述阳极和所述阴极的多晶硅硅化物可编程链路，其中所述阳极和所述多晶硅硅化物可编程链路被其顶部和侧面上的低介电常数（低k）材料围绕。

公开(公告)号：US20090001506A1

公开(公告)日：2009-01-01

申请号：US11771172

申请日：2007-06-29

申请人： Deok-Kee Kim ,  Haining S. Yang

发明人： Deok-Kee Kim ,  Haining S. Yang

IPC分类号： H01L23/52 ,  H01L21/44

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor fuse structure comprises an anode connected to a first end of a fuse link, a cathode connected to a second end of the fuse link opposite the first end of the fuse link, a compressive (nitride) liner covering the anode, and a tensile (nitride) liner covering the cathode. The compressive liner and the tensile liner are positioned to cause a net stress gradient between the cathode and the anode, wherein the net stress gradient promotes electromigration from the cathode and the fuse link to the anode.

摘要翻译： 半导体熔丝结构包括连接到熔丝链的第一端的阳极，与熔丝链的第一端相对的熔断体的第二端连接的阴极，覆盖阳极的压缩（氮化物）衬垫，以及拉伸 （氮化物）衬垫覆盖阴极。 定位压缩衬垫和拉伸衬里以在阴极和阳极之间产生净应力梯度，其中净应力梯度促进从阴极和熔丝连接到阳极的电迁移。

公开(公告)号：US20070259500A1

公开(公告)日：2007-11-08

申请号：US11381861

申请日：2006-05-05

申请人： Kangguo Cheng ,  Oh-Jung Kwon ,  Deok-Kee Kim ,  James Adkisson

发明人： Kangguo Cheng ,  Oh-Jung Kwon ,  Deok-Kee Kim ,  James Adkisson

IPC分类号： H01L21/336 ,  H01L21/76 ,  H01L27/12 ,  H01L27/01 ,  H01L31/0392

CPC分类号： H01L27/1203 ,  H01L21/3003 ,  H01L21/76283 ,  H01L21/823481 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/78654

摘要： Structures having an isolation structure including deuterium and a related method are disclosed. The deuterium is preferably substantially uniformly distributed, and has a concentration (based on total hydrogen atom content) greater than that found in naturally occurring hydrogen. One structure includes a substrate for a semiconductor device including an isolation structure within the substrate, the isolation structure including substantially uniformly distributed deuterium in a concentration (based on total hydrogen atom content) greater than that found in naturally occurring hydrogen. The substrate may include a semiconductor-on-insulator substrate. A method may include the steps of: providing an isolation structure in a substrate, the isolation structure including deuterium; and annealing to diffuse the deuterium into the substrate (prior to and/or after forming a gate dielectric). The structures and method provide a more efficient means for incorporating deuterium and reducing defects. In addition, the deuterium anneal can occur prior to gate dielectric formation during front-end-of-line processes, such that the anneal temperature can be high to improve deuterium incorporation with reduced anneal time.

摘要翻译： 公开了具有包括氘的隔离结构的结构和相关方法。 氘优选基本上均匀分布，并且具有大于在天然存在的氢气中发现的浓度（基于总氢原子含量）。 一种结构包括用于半导体器件的衬底，该衬底包括衬底内的隔离结构，该隔离结构包括基本上均匀分布的氘，其浓度（基于总氢原子含量）大于在天然存在的氢中发现的浓度。 衬底可以包括绝缘体上半导体衬底。 一种方法可以包括以下步骤：在衬底中提供隔离结构，所述隔离结构包括氘; 和退火以将氘扩散到衬底中（在形成栅极电介质之前和/或之后）。 结构和方法提供了一种更有效的方法来引入氘和减少缺陷。 此外，氘退火可以在前端工艺过程中的栅极电介质形成之前发生，使得退火温度可以高以改善氘掺杂并减少退火时间。