公开(公告)号：US08566757B2

公开(公告)日：2013-10-22

申请号：US12609928

申请日：2009-10-30

申请人： Michel L. Cote ,  Christophe Pierrat

发明人： Michel L. Cote ,  Christophe Pierrat

IPC分类号： G06F17/50 ,  G03F1/00

CPC分类号： G03F7/70466 ,  G03F1/26 ,  G03F1/36 ,  G03F1/68 ,  G03F1/70 ,  G03F7/70425 ,  G03F7/70433 ,  G03F7/70558

摘要： A method for defining a full phase layout for defining a layer of material in an integrated circuit is described. The method can be used to define, arrange, and refine phase shifters to substantially define the layer using phase shifting. Through the process, computer readable definitions of an alternating aperture, dark field phase shift mask and of a complimentary mask are generated. Masks can be made from the definitions and then used to fabricate a layer of material in an integrated circuit. The separations between phase shifters, or cuts, are designed for easy mask manufacturability while also maximizing the amount of each feature defined by the phase shifting mask. Cost functions are used to describe the relative quality of phase assignments and to select higher quality phase assignments and reduce phase conflicts.

摘要翻译： 描述了一种用于定义用于在集成电路中定义材料层的全相布局的方法。 该方法可用于定义，排列和细化移相器以基本上使用相移限定层。 通过该过程，产生交替光圈，暗场相移掩模和互补掩模的计算机可读定义。 掩模可以由定义制成，然后用于在集成电路中制造一层材料。 移相器或切口之间的分离被设计为便于掩模制造，同时还使由相移掩模限定的每个特征的量最大化。 成本函数用于描述相位分配的相对质量，并选择较高质量的相位分配并减少相位冲突。

公开(公告)号：US08423924B1

公开(公告)日：2013-04-16

申请号：US13330566

申请日：2011-12-19

申请人： Christophe Pierrat

发明人： Christophe Pierrat

IPC分类号： G06F17/50 ,  G03F1/00

CPC分类号： G06F17/5081 ,  G03F1/36 ,  G03F1/68

摘要： According to various embodiments of the invention, systems and methods for system and methods for compressed post-OPC data created during the design and manufacturing of integrated circuits. In one embodiment of the invention, the method begins by generating a post-OPC layout from a circuit layout during the design phase of a circuit. This post-OPC layout is generated by way of an OPC process. Next, a set of differences between the post-OPC layout and the circuit layout are calculated and a dataset containing these differences are generated In some embodiments the dataset is generated during the OPC process.

公开(公告)号：US20090125867A1

公开(公告)日：2009-05-14

申请号：US12352538

申请日：2009-01-12

申请人： Michel L. Cote ,  Christophe Pierrat

发明人： Michel L. Cote ,  Christophe Pierrat

IPC分类号： G06F17/50

CPC分类号： G03F1/30 ,  G03F1/26 ,  G03F1/36 ,  G03F1/68 ,  G03F7/70425 ,  G03F7/70433 ,  G03F7/70466 ,  G03F7/70558

摘要： Definition of a phase shifting layout from an original layout can be time consuming. If the original layout is divided into useful groups, i.e. clusters that can be independently processed, then the phase shifting process can be performed more rapidly. If the shapes on the layout are enlarged, then the overlapping shapes can be grouped together to identify shapes that should be processed together. For large layouts, growing and grouping the shapes can be time consuming. Therefore, an approach that uses bins can speed up the clustering process, thereby allowing the phase shifting to be performed in parallel on multiple computers. Additional efficiencies result if identical clusters are identified and processing time saved so that repeated clusters of shapes only undergo the computationally expensive phase shifter placement and assignment process a single time.

摘要翻译： 从原始布局定义相移布局可能是耗时的。 如果将原始布局分成有用的组，即可以被独立处理的集群，则可以更快地执行相移过程。 如果布局上的形状被放大，则可以将重叠的形状分组在一起以识别应该一起处理的形状。 对于大型布局，增长和分组形状可能是耗时的。 因此，使用箱体的方法可以加快聚类过程，从而允许在多个计算机上并行执行相移。 如果确定相同的集群并节省处理时间，则可以产生额外的效率，以便重复的形状集群只能在单次时间内经历计算上昂贵的移相器放置和分配过程。

公开(公告)号：US20080286664A1

公开(公告)日：2008-11-20

申请号：US12184215

申请日：2008-07-31

申请人： Christophe Pierrat

发明人： Christophe Pierrat

IPC分类号： G03F1/00

CPC分类号： G03F1/30 ,  G03F1/70

摘要： A full phase shifting mask (FPSM) can be advantageously used in a damascene process for hard-to-etch metal layers. Because the FPSM can be used with a positive photoresist, features on an original layout can be replaced with shifters on a FPSM layout. Adjacent shifters should be of opposite phase, e.g. 0 and 180 degrees. In one embodiment, a dark field trim mask can be used with the FPSM. The trim mask can include cuts that correspond to cuts on the FPSM. Cuts on the FPSM can be made to resolve phase conflicts between proximate shifters. In one case, exposing two proximate shifters on the FPSM and a corresponding cut on the trim mask can form a feature in the metal layer. The FPSM and/or the trim mask can include proximity corrections to further improve printing resolution.

摘要翻译： 全相移掩模（FPSM）可有利地用于难蚀刻金属层的镶嵌工艺。 因为FPSM可以与正光致抗蚀剂一起使用，原始布局上的特征可以用FPSM布局上的移位器替代。 相邻移位器应该是相反的，例如 0和180度。 在一个实施例中，暗场修剪掩模可以与FPSM一起使用。 修剪蒙版可以包括对应于FPSM上的切割的切口。 可以对FPSM进行切割以解决相邻移位器之间的相位冲突。 在一种情况下，在FPSM上曝光两个相邻的移位器并且在修剪蒙版上相应的切割可以在金属层中形成特征。 FPSM和/或修剪掩模可以包括接近校正以进一步提高打印分辨率。

公开(公告)号：US07348108B2

公开(公告)日：2008-03-25

申请号：US10938653

申请日：2004-09-10

申请人： Michel L. Cote ,  Christophe Pierrat

发明人： Michel L. Cote ,  Christophe Pierrat

IPC分类号： G03F1/00 ,  G03B27/42

CPC分类号： G03F7/70466 ,  G03F1/26 ,  G03F1/36 ,  G03F1/68 ,  G03F1/70 ,  G03F7/70425 ,  G03F7/70433 ,  G03F7/70558

摘要： A method for defining a full phase layout for defining a layer of material in an integrated circuit is described. The method can be used to define, arrange, and refine phase shifters to substantially define the layer using phase shifting. Through the process, computer readable definitions of an alternating aperture, dark field phase shift mask and of a complimentary mask are generated. Masks can be made from the definitions and then used to fabricate a layer of material in an integrated circuit. The separations between phase shifters, or cuts, are designed for easy mask manufacturability while also maximizing the amount of each feature defined by the phase shifting mask. Cost functions are used to describe the relative quality of phase assignments and to select higher quality phase assignments and reduce phase conflicts.

公开(公告)号：US07178128B2

公开(公告)日：2007-02-13

申请号：US10272104

申请日：2002-10-15

申请人： Hua-Yu Liu ,  Christophe Pierrat ,  Kent Richardson

发明人： Hua-Yu Liu ,  Christophe Pierrat ,  Kent Richardson

IPC分类号： G06F17/50

CPC分类号： G03F1/30

摘要： Methods and apparatuses for preparing layouts and masks that use phase shifting to enable production of subwavelength features on an integrated circuit in close (optical) proximity to other structures are described. One embodiment selects from several strategies for resolving conflicts between phase shifters used to define features and (optically) proximate structures that are being defined other than by phase shifting. One embodiment adds additional phase shifters to define the conflicting structures. Another embodiment corrects the shape of the phase shifters in proximity to a conflicting structure. Resulting integrated circuits can include a greater number of subwavelength features even in areas that are in close proximity to structures that were not initially identified for production using a phase shifting mask.

摘要翻译： 描述了用于制备使用相移的布局和掩模的方法和装置，以使得能够在紧密（光学）接近其它结构的集成电路上产生亚波长特征。 一个实施例从用于解决用于定义特征的移相器之间的冲突的几种策略中选择（以光学方式）除了通过相移之外定义的邻近结构之间的冲突。 一个实施例增加了附加移相器来定义冲突结构。 另一个实施例校正了相邻结构附近的移相器的形状。 所得到的集成电路可以包括更多数量的亚波长特征，即使在与初始识别用于使用相移掩模生产的结构非常接近的区域中。

公开(公告)号：US07083879B2

公开(公告)日：2006-08-01

申请号：US09932239

申请日：2001-08-17

申请人： Christophe Pierrat ,  Michel Luc Côté

发明人： Christophe Pierrat ,  Michel Luc Côté

IPC分类号： G03F9/00 ,  G06F17/50

CPC分类号： G03F7/70466 ,  G03F1/26 ,  G03F7/70425 ,  G03F7/70433 ,  G03F7/70558

摘要： A photolithographic mask used for defining a layer in an integrated circuit, or other work piece, where the layer comprises a pattern including a plurality of features to be implemented with phase shifting in phase shift regions is laid out including for patterns comprising high density, small dimension features, and for “full shift” patterns. The method includes identifying cutting areas for phase shift regions based on characteristics of the pattern. Next, the process cuts the phase shift regions in selected ones of the cutting areas to define phase shift windows, and assigns phase values to the phase shift windows. The phase shift values assigned comprise φ and θ, so that destructive interference is caused in transitions between adjacent phase shift windows having respective phase shift values of φ and θ. In the preferred embodiment, φ is equal to approximately θ+180 degrees. Results of the cutting and assigning steps are stored in a computer readable medium, used for manufacturing a mask, and used for manufacturing an integrated circuit. By identifying the cutting areas based on characteristics of the pattern to be formed, the problem of dividing phase shift regions into phase shift windows, and assigning phase shift values to the windows is simplified.

公开(公告)号：US07071058B2

公开(公告)日：2006-07-04

申请号：US10817548

申请日：2004-04-02

申请人： Martin Ceredig Roberts ,  Christophe Pierrat

发明人： Martin Ceredig Roberts ,  Christophe Pierrat

IPC分类号： H01L21/8242 ,  H01L21/20

CPC分类号： H01L27/10855 ,  H01L28/91

摘要： Capacitors, DRAM circuitry, and methods of forming the same are described. In one embodiment, a capacitor comprises a first container which is joined with a substrate node location and has an opening defining a first interior area. A second container is joined with the node location and has an opening defining a second interior area. The areas are spaced apart from one another in a non-overlapping relationship. A dielectric layer and a conductive capacitor electrode layer are disposed operably proximate the first and second containers. In another embodiment, the first and second containers are generally elongate and extend away from the node location along respective first and second central axes. The axes are different and spaced apart from one another. In yet another embodiment, a conductive layer of material is disposed over and in electrical communication with a substrate node location. The layer of material has an outer surface with a first region and a second region spaced apart from the first region. A first container is formed over and in electrical communication with the first region and a second container is formed over and in electrical communication with the second region. In yet another embodiment, the first and second containers define container volumes which are discrete and separated from one another.

摘要翻译： 描述了电容器，DRAM电路及其形成方法。 在一个实施例中，电容器包括与衬底节点位置连接并具有限定第一内部区域的开口的第一容器。 第二容器与节点位置连接并且具有限定第二内部区域的开口。 这些区域以不重叠的关系彼此间隔开。 电介质层和导电电容器电极层可操作地设置在第一和第二容器的附近。 在另一个实施例中，第一和第二容器通常是细长的并且沿相应的第一和第二中心轴线远离节点位置延伸。 轴是不同的并且彼此间隔开。 在另一个实施例中，材料的导电层设置在衬底节点位置上并与衬底节点位置电连通。 材料层具有外表面，其具有第一区域和与第一区域间隔开的第二区域。 第一容器形成在第一区域之上并与第一区域电连通，并且第二容器形成在第二区域上并与第二区域电连通。 在另一个实施例中，第一和第二容器限定彼此离散和分离的容器体积。

公开(公告)号：US07052617B2

公开(公告)日：2006-05-30

申请号：US10318021

申请日：2002-12-13

申请人： Karen Huang ,  Christophe Pierrat

发明人： Karen Huang ,  Christophe Pierrat

IPC分类号： H01L21/302

CPC分类号： H01J9/24 ,  H01J9/025 ,  H01J29/481 ,  H01J31/127

摘要： A process for producing multiple undercut profiles in a single material. A resist pattern is applied over a work piece and a wet etch is performed to produce an undercut in the material. This first wet etch is followed by a polymerizing dry etch that produces a polymer film in the undercut created by the first wet etch. The polymer film prevents further etching of the undercut portion during a second wet etch. Thus, an undercut profile can be obtained having a larger undercut in an underlying portion of the work piece, utilizing only a single resist application step. The work piece may be a multi-layer work piece having different layers formed of the same material, or it may be a single layer of material.

摘要翻译： 用于在单一材料中生产多个底切轮廓的方法。 将抗蚀剂图案施加在工件上，并进行湿蚀刻以在材料中产生底切。 该第一次湿蚀刻之后是聚合干蚀刻，其通过第一次湿蚀刻产生的底切中产生聚合物膜。 聚合物膜在第二次湿法蚀刻期间防止进一步蚀刻底切部分。 因此，可以仅利用单个抗蚀剂涂敷步骤，在工件的下面部分中获得具有较大底切的底切轮廓。 工件可以是具有由相同材料形成的不同层的多层工件，或者它可以是单层材料。

公开(公告)号：US07003757B2

公开(公告)日：2006-02-21

申请号：US10855673

申请日：2004-05-26

申请人： Christophe Pierrat ,  Youping Zhang

发明人： Christophe Pierrat ,  Youping Zhang

IPC分类号： G06F17/50 ,  G03C5/00

CPC分类号： G03F1/36 ,  G03F7/70441

摘要： Techniques for fabricating a device include forming a fabrication layout, such as a mask layout, for a physical design layer, such as a design for an integrated circuit, and identifying evaluation points on an edge of a polygon corresponding to the design layer for correcting proximity effects. Techniques include selecting from among all edges of all polygons in a proposed layout a subset of edges for which proximity corrections are desirable. The subset of edges includes less than all the edges. Evaluation points are established only for the subset of edges. Corrections are determined for at least portions of the subset of edges based on an analysis performed at the evaluation points. Other techniques include establishing a projection point on a first edge corresponding to the design layout based on whether a vertex of a second edge is within a halo distance. An evaluation point is determined for the first edge based on the projection point and characteristics of the first edge. It is then determined how to correct at least a portion of the edge for proximity effects based on an analysis at the evaluation point.

摘要翻译： 用于制造器件的技术包括形成用于物理设计层（例如集成电路的设计）的制造布局，例如掩模布局，以及识别与设计层对应的多边形的边缘上的评估点，用于校正接近度 效果。 技术包括在所提出的布局中从所有多边形的所有边缘中选择需要接近校正的边缘子集。 边缘子集包括少于所有边缘。 仅针对边缘子集建立评估点。 基于在评估点执行的分析，确定边缘子集的至少部分的校正。 其他技术包括基于第二边缘的顶点是否在光晕距离内，在对应于设计布局的第一边缘上建立投影点。 基于投影点和第一边缘的特性，确定第一边缘的评估点。 然后基于评估点的分析确定如何校正边缘的至少一部分以用于邻近效应。