公开(公告)号：USD689039S1

公开(公告)日：2013-09-03

申请号：US29427014

申请日：2012-07-12

申请人： Hua-Yu Liu

设计人： Hua-Yu Liu

公开(公告)号：US20130212543A1

公开(公告)日：2013-08-15

申请号：US13753401

申请日：2013-01-29

申请人： Michael Matthew M. CROUSE ,  Youri Johannes Laurentius Maria VAN DOMMELEN ,  Peng LIU ,  Hua-Yu LIU ,  Aiqin JIANG ,  Wenjin HUANG

发明人： Michael Matthew M. CROUSE ,  Youri Johannes Laurentius Maria VAN DOMMELEN ,  Peng LIU ,  Hua-Yu LIU ,  Aiqin JIANG ,  Wenjin HUANG

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G03F7/70125 ,  G03F7/70433 ,  G03F7/705 ,  G03F7/70891

摘要： A computer-implemented method for improving a lithographic process for imaging a portion of a design layout onto a substrate using a lithographic projection apparatus comprising an illumination source and projection optics, the method including computing a multi-variable cost function of a plurality of design variables that are characteristics of the lithographic process, at least some of the design variables being characteristics of the illumination source and the design layout, the computing of the multi-variable cost function accounting for lens heating effects; and reconfiguring the characteristics of the lithographic process by adjusting the design variables until a predefined termination condition is satisfied.

摘要翻译： 一种用于改进用于使用包括照明源和投影光学器件的光刻投影装置将设计布局的一部分成像到基板上的光刻处理的计算机实现的方法，所述方法包括计算多个设计变量的多变量成本函数 这是光刻过程的特征，至少一些设计变量是照明源的特征和设计布局，计算多变量成本函数来计算透镜加热效应; 并且通过调整设计变量来重新配置光刻处理的特性，直到满足预定的终止条件。

公开(公告)号：US08438508B2

公开(公告)日：2013-05-07

申请号：US12914946

申请日：2010-10-28

申请人： Hua-Yu Liu

发明人： Hua-Yu Liu

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G03F1/144 ,  G03F1/36 ,  G03F7/70125 ,  G03F7/70425 ,  G03F7/70441 ,  G03F7/705 ,  G03F7/70666 ,  G06F17/50 ,  G06F17/5009

摘要： The present invention relates to lithographic apparatuses and processes, and more particularly to tools for optimizing illumination sources and masks for use in lithographic apparatuses and processes. According to certain aspects, the present invention enables full chip pattern coverage while lowering the computation cost by intelligently selecting a small set of critical design patterns from the full set of clips to be used in source and mask optimization. Optimization is performed only on these selected patterns to obtain an optimized source. The optimized source is then used to optimize the mask (e.g. using OPC and manufacturability verification) for the full chip, and the process window performance results are compared. If the results are comparable to conventional full-chip SMO, the process ends, otherwise various methods are provided for iteratively converging on the successful result.

摘要翻译： 本发明涉及光刻设备和工艺，更具体地涉及用于优化用于光刻设备和工艺的照明源和掩模的工具。 根据某些方面，本发明通过从源和掩码优化中使用的全套剪辑智能地选择一小组关键设计模式来实现全芯片模式覆盖，同时降低计算成本。 仅对这些选择的模式执行优化以获得优化的源。 然后优化的源用于优化全芯片的掩模（例如使用OPC和可制造性验证），并比较处理窗口性能结果。 如果结果与传统的全芯片SMO相当，则过程结束，否则提供了各种方法来迭代地收敛成功的结果。

公开(公告)号：US06684382B2

公开(公告)日：2004-01-27

申请号：US09945012

申请日：2001-08-31

申请人： Hua-Yu Liu

发明人： Hua-Yu Liu

IPC分类号： G06F1750

CPC分类号： G03F1/36 ,  G03F1/68

摘要： A method and apparatus for providing correction for microloading effects is described. Hybrid proximity correction techniques are used to make the problem computationally more feasible. More specifically, feature edges in a layout can be grouped into those edges, or edge segments, with a large edge separation (group B), e.g. greater than n, and those having less than that separation (group A). The group B features can then be corrected for microloading effects rapidly using rules based correction. Then both groups of edges can be corrected using model based optical proximity correction using the output of the rule based correction as the ideal, or reference, layout.

摘要翻译： 描述了一种用于提供微载荷效应校正的方法和装置。 混合接近校正技术用于使问题在计算上更可行。 更具体地，布局中的特征边缘可以被分组成具有大边缘分离（组B）的那些边缘或边缘片段。 大于n，且具有小于该分离的那些（A组）。 然后可以使用基于规则的校正快速校正组B特征。 然后，使用基于规则的校正的输出作为理想或参考布局，可以使用基于模型的光学邻近校正来校正两组边缘。

公开(公告)号：US06664009B2

公开(公告)日：2003-12-16

申请号：US09917581

申请日：2001-07-27

申请人： Hua-Yu Liu

发明人： Hua-Yu Liu

IPC分类号： G03F900

CPC分类号： G03F1/30 ,  G03F1/70

摘要： Phase shifting layouts and masks with phase conflicts are described. The phase shifting layout defines light transmissive regions for use in defining selected features in a layer of material of an integrated circuit (IC). The phase shifting layout includes a phase conflict caused by two light transmissive regions that are out of phase with each other and which, without correction, would lead to the definition of an artifact in the layer of material. A corresponding mask adapted for use in conjunction with the phase shifting mask can ensure that the artifact is ultimately erased. The phase conflict is intentionally introduced into the phase shifting layout during phase assignment to permit all of the selected features to be defined using the phase shifting mask.

公开(公告)号：US06573010B2

公开(公告)日：2003-06-03

申请号：US09843487

申请日：2001-04-25

申请人： Michael E. Kling ,  Hua-Yu Liu

发明人： Michael E. Kling ,  Hua-Yu Liu

IPC分类号： G03F900

CPC分类号： G03F1/30 ,  G03F1/36 ,  G03F1/70

摘要： One embodiment of the invention provides a system for reducing incidental exposure caused by phase shifting during fabrication of a semiconductor chip. The system operates by identifying a problem area of likely incidental exposure in close proximity to an existing phase shifter on a phase shifting mask, wherein the problem area includes a polysilicon line passing through a field region of the semiconductor chip. The system places an additional phase shifter into the problem area on the phase shifting mask so that a regulator within the additional phase shifter protects the polysilicon line passing through the field region. This additional phase shifter has a wider regulator than the existing phase shifter, wherein the existing phase shifter is used to expose a polysilicon line in a gate region of the semiconductor chip.

公开(公告)号：US06553560B2

公开(公告)日：2003-04-22

申请号：US09872620

申请日：2001-05-31

申请人： Melody W. Ma ,  Hua-Yu Liu

发明人： Melody W. Ma ,  Hua-Yu Liu

IPC分类号： G06F1750

CPC分类号： G03F1/30 ,  G03F1/36

摘要： One embodiment of the invention provides a system and a method for reducing line end shortening during an optical lithography process for manufacturing an integrated circuit. The system operates by receiving a specification of the integrated circuit, wherein the specification defines transistors that include gates. Next, the system identifies a gate within the specification, wherein the gate includes an endcap that is susceptible to line end shortening during the optical lithography process. The system then extends a phase shifter used to form the gate, so that the phase shifter defines at least a portion of the endcap and thereby reduces line end shortening of the endcap due to optical effects.

公开(公告)号：US08887104B2

公开(公告)日：2014-11-11

申请号：US13823685

申请日：2011-09-01

申请人： Hua-Yu Liu ,  Jiangwei Li ,  Luoqi Chen ,  Wei Liu ,  Jiong Jiang

发明人： Hua-Yu Liu ,  Jiangwei Li ,  Luoqi Chen ,  Wei Liu ,  Jiong Jiang

IPC分类号： G06F17/50 ,  G03F7/20

CPC分类号： G06F17/5045 ,  G03F7/705 ,  G03F7/70941 ,  G06F17/5009

摘要： A method for reducing an effect of flare produced by a lithographic apparatus for imaging a design layout onto a substrate is described. A flare map in an exposure field of the lithographic apparatus is simulated by mathematically combining a density map of the design layout at the exposure field with a point spread function (PSF), wherein system-specific effects on the flare map may be incorporated in the simulation. Location-dependent flare corrections for the design layout are calculated by using the determined flare map, thereby reducing the effect of flare. Some of the system-specific effects included in the simulation are: a flare effect due to reflection from black border of a mask, a flare effect due to reflection from one or more reticle-masking blades defining an exposure slit, a flare effect due to overscan, a flare effect due reflections from a gas-lock sub-aperture of a dynamic gas lock (DGL) mechanism, and a flare effect due to contribution from neighboring exposure fields.

摘要翻译： 描述了一种用于降低由用于将设计布局成像到基板上的光刻设备产生的火炬的影响的方法。 通过将曝光场上的设计布局的密度图与点扩散函数（PSF）进行数学组合来模拟光刻设备的曝光区域中的耀斑图，其中可以在闪光图中对系统特定的影响 模拟。 通过使用确定的耀斑图计算设计布局的位置相关的光斑校正，从而减少了耀斑的影响。 仿真中包括的一些系统特定效果是：由于掩模的黑色边缘的反射引起的耀斑效应，由于限定曝光狭缝的一个或多个掩模版掩模片的反射引起的耀斑效应，由于 过扫描，来自动态气体锁（DGL）机构的气体锁定子孔的反射引起的闪光效应，以及由于来自相邻曝光场的贡献而产生的耀斑效果。

公开(公告)号：US07178128B2

公开(公告)日：2007-02-13

申请号：US10272104

申请日：2002-10-15

申请人： Hua-Yu Liu ,  Christophe Pierrat ,  Kent Richardson

发明人： Hua-Yu Liu ,  Christophe Pierrat ,  Kent Richardson

IPC分类号： G06F17/50

CPC分类号： G03F1/30

摘要： Methods and apparatuses for preparing layouts and masks that use phase shifting to enable production of subwavelength features on an integrated circuit in close (optical) proximity to other structures are described. One embodiment selects from several strategies for resolving conflicts between phase shifters used to define features and (optically) proximate structures that are being defined other than by phase shifting. One embodiment adds additional phase shifters to define the conflicting structures. Another embodiment corrects the shape of the phase shifters in proximity to a conflicting structure. Resulting integrated circuits can include a greater number of subwavelength features even in areas that are in close proximity to structures that were not initially identified for production using a phase shifting mask.

摘要翻译： 描述了用于制备使用相移的布局和掩模的方法和装置，以使得能够在紧密（光学）接近其它结构的集成电路上产生亚波长特征。 一个实施例从用于解决用于定义特征的移相器之间的冲突的几种策略中选择（以光学方式）除了通过相移之外定义的邻近结构之间的冲突。 一个实施例增加了附加移相器来定义冲突结构。 另一个实施例校正了相邻结构附近的移相器的形状。 所得到的集成电路可以包括更多数量的亚波长特征，即使在与初始识别用于使用相移掩模生产的结构非常接近的区域中。

公开(公告)号：US06830854B2

公开(公告)日：2004-12-14

申请号：US10685751

申请日：2003-10-14

申请人： Yong Liu ,  Hua-Yu Liu

发明人： Yong Liu ,  Hua-Yu Liu

IPC分类号： G03F900

CPC分类号： G03F1/30 ,  G03F1/36

摘要： An accurate, cost-effective system and method for correcting 3D effects on an alternating phase-shifting mask (PSM) is provided. To facilitate this correction, a library can be built to include a first group of 180 degree phase-shifting regions, wherein these regions have a common first size. Based on this first size, 3D simulation is performed. A transmission and a phase are altered in a 2D simulation based on this first size until a shape dependent transmission and a shape dependent phase allow the 2D simulation to substantially match the 3D simulation. Finally, a modified first size is chosen using the shape dependent transmission and the shape dependent phase such that a 2D simulation based on the modified first size substantially matches the 3D simulation based on the first size. The library associates the first size with the modified first size, the shape dependent transmission, and the shape dependent phase.

摘要翻译： 提供了一种用于校正交替相移掩模（PSM）上的3D效果的准确，经济有效的系统和方法。 为了便于该校正，可以构建库以包括第一组180度相移区域，其中这些区域具有共同的第一尺寸。 基于该第一尺寸，进行3D模拟。 在基于该第一尺寸的2D模拟中改变传输和相位，直到形状相关传输和形状相关相位允许2D模拟基本上匹配3D模拟。 最后，使用形状依赖的传输和形状相关的相位来选择修改的第一尺寸，使得基于修改后的第一尺寸的2D模拟基于第一尺寸基本匹配3D模拟。 该库将第一个大小与修改的第一个大小，形状相关的传输和形状依赖相关联。