公开(公告)号：US06764911B2

公开(公告)日：2004-07-20

申请号：US10143227

申请日：2002-05-10

申请人： Jw-Wang Hsu ,  Ming-Huan Tsai ,  Mei-Ru Kuo ,  Baw-Ching Peng ,  Hun-Jan Tao

发明人： Jw-Wang Hsu ,  Ming-Huan Tsai ,  Mei-Ru Kuo ,  Baw-Ching Peng ,  Hun-Jan Tao

IPC分类号： H01L21336

CPC分类号： H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： Within a method for forming a spacer layer from a second layer formed of a second material laminated upon a first layer formed of a first material, in turn formed over a topographic feature, there is employed a three step etch method. The three step etch method employs: (1) a first etch method having a first enhanced etch selectivity for the second material with respect to the first material; (2) a second etch method having a second substantially neutral etch selectivity for the second material with respect to the first material; and (3) a third etch method having a third enhanced etch selectivity for the first material with respect to the second material. In accord with the three step etch method, the spacer layer is fabricated with enhanced dimensional control.

摘要翻译： 在由层压在由第一材料形成的第一层上的第二材料形成的第二层形成间隔层的方法中，依次形成在地形特征上，采用三步骤蚀刻方法。 三步骤蚀刻方法采用：（1）第一蚀刻方法相对于第一材料具有对第二材料的第一增强蚀刻选择性; （2）对于第二材料相对于第一材料具有第二基本中性蚀刻选择性的第二蚀刻方法; 和（3）第三蚀刻方法，其相对于第二材料具有第一材料的第三增强蚀刻选择性。 根据三步蚀刻方法，间隔层用增强的尺寸控制制造。

公开(公告)号：US06368974B1

公开(公告)日：2002-04-09

申请号：US09365416

申请日：1999-08-02

申请人： Ming-Huan Tsai ,  Chan-Lon Yang

发明人： Ming-Huan Tsai ,  Chan-Lon Yang

IPC分类号： H01L21311

CPC分类号： H01L21/31144

摘要： A method for shrinking equivalent critical dimension of mask by in situ polymer deposition and etching is proposed. The invention comprises following key points: First, when a photo-resist is formed on a substrate by a mask and a photolithography process, a polymer layer is formed on said photo-resist. Second, a plasma reactor with at least two independent power sources is used to form and etch the polymer layer, where ion density and ion energy of plasma are adjusted respectively by different power sources. Third, voltages of all power sources are adjusted such that etching rate and depositing rate are equivalent on surface of the photo-resist and etching rate is obviously larger than depositing rate in bottom of any structure of the photo-resist. Therefore, the sidewall of any structure is filled by a conformal polymer layer and then width of any structure is efficiently decreased. By the way, the critical dimension of any structure is significant smaller than critical dimension of the mask. In other words, equivalent critical dimension of mask is shrunk by the invention. Obviously, the photo-resist with shrunk critical dimension can be used to form semiconductor device with critical dimension that is more narrow than critical dimension of the mask.

摘要翻译： 提出了通过原位聚合物沉积和蚀刻收缩掩模的等效临界尺寸的方法。 本发明包括以下要点：首先，通过掩模和光刻工艺在基板上形成光致抗蚀剂时，在所述光致抗蚀剂上形成聚合物层。 其次，使用具有至少两个独立电源的等离子体反应器来形成和蚀刻聚合物层，其中等离子体的离子密度和离子能分别由不同的电源调节。 第三，调整所有电源的电压，使得蚀刻速率和沉积速率在光刻胶的表面上相当，并且蚀刻速率明显大于光刻胶的任何结构的底部的沉积速率。 因此，任何结构的侧壁由保形聚合物层填充，然后任何结构的宽度被有效地降低。 顺便说一句，任何结构的临界尺寸都明显小于掩模的临界尺寸。 换句话说，本发明缩小了掩模的等效临界尺寸。 显然，具有缩小的临界尺寸的光刻胶可用于形成临界尺寸比掩模的临界尺寸更窄的半导体器件。

公开(公告)号：US07115526B2

公开(公告)日：2006-10-03

申请号：US10101076

申请日：2002-03-18

申请人： Hsieh Yue Ho ,  Chih-Cheng Wang ,  Hsiao Shih-Yi ,  Kang Tsung-Kuei ,  Bing-Yue Tsui ,  Chih-Feng Huang ,  Jann-Shyang Liang ,  Ming-Huan Tsai ,  Hun-Jan Tao ,  Baw-ching Perng

发明人： Hsieh Yue Ho ,  Chih-Cheng Wang ,  Hsiao Shih-Yi ,  Kang Tsung-Kuei ,  Bing-Yue Tsui ,  Chih-Feng Huang ,  Jann-Shyang Liang ,  Ming-Huan Tsai ,  Hun-Jan Tao ,  Baw-ching Perng

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/31111 ,  H01L21/31641 ,  H01L21/31645 ,  H01L27/10814 ,  H01L27/10852 ,  H01L28/40

摘要： The present invention discloses an electrode structure of a light emitted diode and manufacturing method of the electrodes. After formed a pn junction of a light emitted diode on a substrate, a layer of SiO2 is deposited on the periphery of the die of the LED near the scribe line of the wafer, then a transparent conductive layer is deposited blanketly, then a layer of gold or AuGe etc. is formed with an opening on the center of the die. After forming alloy with the semiconductor by heat treatment to form ohmic contact, a strip of aluminum (Al) is formed on one side of the die on the front side for wire bonding and to be the positive electrode of the LED. The negative electrode is formed on the substrate by metal contact. Another form of the electrode structure of the present invention is making both the positive and negative electrodes on the front side of the LED by etching the p-type semiconductor of the pn junction and forming a strip of negative electrode on the n-type semiconductor, the positive electrode is formed on the p-type semiconductor.

公开(公告)号：US06878639B1

公开(公告)日：2005-04-12

申请号：US10667013

申请日：2003-09-19

申请人： Ming-Huan Tsai ,  Ru-Chian Chiang ,  Hun-Jan Tao

发明人： Ming-Huan Tsai ,  Ru-Chian Chiang ,  Hun-Jan Tao

IPC分类号： H01L21/302 ,  H01L21/311 ,  H01L21/60

CPC分类号： H01L21/76897 ,  H01L21/31105 ,  H01L21/31116

摘要： A new method for fabricating a borderless interconnection in a semiconductor device is provided. During fabrication, the device includes an interlevel dielectric (ILD) layer, a metal silicide layer, and a stop layer disposed between the ILD and metal silicide layers. The stop layer may be formed of silicon nitride or silicon oxynitride, and the metal silicide layer may be a nickel silicide. The method includes etching the ILD layer to expose at least a portion of the stop layer and then performing a nitrogen plasma treatment on the exposed portion of the stop layer. After the treatment, the exposed portion of the stop layer is removed to provide the interconnection hole. Because of the plasma treatment, damage to the metal silicide underlying the stop layer will be minimized when the stop layer is removed.

摘要翻译： 提供了一种在半导体器件中制造无边界互连的新方法。 在制造期间，器件包括层间电介质（ILD）层，金属硅化物层和设置在ILD和金属硅化物层之间的阻挡层。 阻挡层可以由氮化硅或氮氧化硅形成，并且金属硅化物层可以是硅化镍。 该方法包括蚀刻ILD层以暴露停止层的至少一部分，然后在停止层的暴露部分上进行氮等离子体处理。 在处理之后，去除停止层的暴露部分以提供互连孔。 由于等离子体处理，当停止层被去除时，对停止层下面的金属硅化物的损坏将被最小化。

公开(公告)号：US06787455B2

公开(公告)日：2004-09-07

申请号：US10032353

申请日：2001-12-21

申请人： Ming-Huan Tsai ,  Hun-Jan Tao ,  Ju-Wang Hsu ,  Cheng-Ku Chen

发明人： Ming-Huan Tsai ,  Hun-Jan Tao ,  Ju-Wang Hsu ,  Cheng-Ku Chen

IPC分类号： H01L214763

CPC分类号： G03F7/094 ,  H01L21/0274 ,  H01L21/76802

摘要： A method for semiconductor device feature development using a bi-layer photoresist including providing a non-silicon containing photoresist layer over a substrate; providing a silicon containing photoresist over the non-silicon containing photoresist layer; exposing said silicon containing photoresist layer to an activating light source an exposure surface defined by an overlying pattern according to a photolithographic process; developing said silicon containing photoresist layer according to a photolithographic process to reveal a portion the non-silicon containing photoresist layer; and, dry developing said non-silicon containing photoresist layer in a plasma reactor by igniting a plasma from an ambient mixture including at least oxygen, carbon monoxide, and argon.

摘要翻译： 一种使用双层光致抗蚀剂的半导体器件特征显影的方法，包括在衬底上提供不含硅的光致抗蚀剂层; 在含硅光致抗蚀剂层上提供含硅光致抗蚀剂; 将所述含硅光致抗蚀剂层暴露于激活光源，根据光刻工艺由覆盖图案限定的曝光表面; 根据光刻工艺显影所述含硅光致抗蚀剂层以露出含有非硅的光致抗蚀剂层的一部分; 以及通过从包括至少氧，一氧化碳和氩的环境混合物点燃等离子体，在等离子体反应器中干燥显影所述不含硅的光致抗蚀剂层。

公开(公告)号：US06399437B1

公开(公告)日：2002-06-04

申请号：US09099258

申请日：1998-06-18

申请人： Yung-Yi Hsu ,  Yi-Tsai Yi ,  Chia-Shun Hsiao ,  Ming-Huan Tsai

发明人： Yung-Yi Hsu ,  Yi-Tsai Yi ,  Chia-Shun Hsiao ,  Ming-Huan Tsai

IPC分类号： H01L218242

CPC分类号： H01L28/87 ,  H01L28/91

摘要： A method of forming a stacked capacitor having improved capacitance in a dynamic random access memory device is provided wherein and additional pad polysilicon layer is deposited prior to the forming of the capacitor cell contact area such that the side-wall of the capacitor cell can be increased. The increased side-wall thickness of the capacitor cell leads to an improved capacitance value for the cell. The present invention also provides a stacked capacitor formed in a semiconductor device that contains an additional pad polysilicon layer for increasing the thickness of the capacitor side-wall and subsequently its capacitance.

摘要翻译： 提供了一种在动态随机存取存储器件中形成具有改善的电容的叠层电容器的方法，其中在形成电容器单元接触区域之前淀积另外的焊盘多晶硅层，使得电容器单元的侧壁可以增加 。 电容器单元的增加的侧壁厚度导致电池的电容值改善。 本发明还提供一种形成在半导体器件中的堆叠电容器，其包含用于增加电容器侧壁的厚度和随后的电容的附加焊盘多晶硅层。

公开(公告)号：US06251791B1

公开(公告)日：2001-06-26

申请号：US09357246

申请日：1999-07-20

申请人： Ming-Huan Tsai ,  Chan-Lon Yang

发明人： Ming-Huan Tsai ,  Chan-Lon Yang

IPC分类号： H01L21311

CPC分类号： H01L21/31144 ,  H01L21/31116

摘要： A method for eliminating the etching microloading effect is proposed for the invention. Spirit of the invention is that a coating layer is formed on a photo-resist that covers a substrate before the substrate is etched, where coating layer maybe a polymer layer or a dielectric layer. Because step coverage of the coating layer is limited by the aspect of trench, for photo-resist it means the width of openings, it is indisputable that depth of coating layer on bottom of a narrow opening is smaller than depth of coating layer on bottom of a wide opening. Therefore, during following etching process, although etching microloading effect induces etching rate is higher in the wide opening and is lower in the narrow opening, but the thicker coating layer on bottom of the wide opening also requires larger etching time than the narrow opening. Consequently, it is crystal-clear that the etching microloading effect is cancelled and then depth of the wide trench is equal to depth of the narrow trench.

摘要翻译： 本发明提出了一种消除蚀刻微加载效应的方法。 本发明的精神是在蚀刻基板之前在覆盖基板的光致抗蚀剂上形成涂层，其中涂层可以是聚合物层或电介质层。 由于涂层的层间覆盖受到沟槽的限制，对于光刻胶而言，它意味着开口的宽度，不可否认，窄开口底部的涂层深度小于底部的涂层深度 一个广阔的开幕 因此，在随后的蚀刻过程中，虽然蚀刻微加载效应导致在宽开口中的蚀刻速率较高，而在窄开口中蚀刻速率较低，但是宽开口底部较厚的涂层也需要比窄开口更大的蚀刻时间。 因此，清楚的是蚀刻微加载效应被消除，然后宽沟槽的深度等于窄沟槽的深度。