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    LOGICAL TO PHYSICAL ADDRESS MAPPING IN STORAGE SYSTEMS COMPRISING SOLID STATE MEMORY DEVICES
    43.
    发明申请
    LOGICAL TO PHYSICAL ADDRESS MAPPING IN STORAGE SYSTEMS COMPRISING SOLID STATE MEMORY DEVICES 有权
    在包含固态存储器件的存储系统中逻辑地址映射

    公开(公告)号：US20130124794A1

    公开(公告)日：2013-05-16

    申请号：US13812377

    申请日：2011-07-25

    申请人： Werner Bux ,  Robert Haas ,  Xiao-Yu Hu ,  Roman Pletka

    发明人： Werner Bux ,  Robert Haas ,  Xiao-Yu Hu ,  Roman Pletka

    IPC分类号： G06F12/02

    CPC分类号： G06F12/0246 ,  G06F12/0848 ,  G06F12/0866 ,  G06F2212/214 ,  G06F2212/221 ,  G06F2212/222 ,  G06F2212/466 ,  G06F2212/7201

    摘要： The present idea provides a high read and write performance from/to a solid state memory device. The main memory of the controller is not blocked by a complete address mapping table covering the entire memory device. Instead such table is stored in the memory device itself, and only selected portions of address mapping information are buffered in the main memory in a read cache and a write cache. A separation of the read cache from the write cache enables an address mapping entry being evictable from the read cache without the need to update the related flash memory page storing such entry in the flash memory device. By this design, the read cache may advantageously be stored on a DRAM even without power down protection, while the write cache may preferably be implemented in nonvolatile or other fail-safe memory. This leads to a reduction of the overall provisioning of nonvolatile or fail-safe memory and to an improved scalability and performance.

    摘要翻译： 本想法提供了从/到固态存储器件的高读/写性能。 控制器的主存储器不被覆盖整个存储器件的完整地址映射表阻止。 相反，这样的表被存储在存储器设备本身中，并且只有地址映射信息的选定部分被缓存在读取高速缓存和写入高速缓存中的主存储器中。 读取高速缓存与写入高速缓存的分离使得能够从读取的高速缓存中取出地址映射条目，而不需要在闪存设备中更新存储这样的条目的相关闪存页面。 通过这种设计，读取高速缓存可以有利地存储在DRAM上，即使没有掉电保护，而写入高速缓存也可以优选地被实现在非易失性或其它故障安全存储器中。 这导致了非易失性或故障安全存储器的总体配置的减少以及改进的可扩展性和性能。

    FLASH MEMORY CONTROLLER
    45.
    发明申请
    FLASH MEMORY CONTROLLER 有权
    闪存控制器

    公开(公告)号：US20120278544A1

    公开(公告)日：2012-11-01

    申请号：US13515118

    申请日：2010-12-09

    申请人： Evangelos S. Eleftheriou ,  Robert Haas ,  Xiao-Yu Hu

    发明人： Evangelos S. Eleftheriou ,  Robert Haas ,  Xiao-Yu Hu

    IPC分类号： G06F12/02

    CPC分类号： G06F13/1668 ,  G06F9/3004 ,  G11C7/1042

    摘要： A Flash memory controller is coupled to a first Flash memory package through a first Flash memory interface and to a second Flash memory package through the first Flash memory interface. The Flash memory controller is designed to receive a first instruction relating to the first Flash memory package and to perform a first process depending on the first instruction. The Flash memory controller is further designed to receive a second instruction relating to the second Flash memory package and to perform a second process depending on the second instruction. The Flash memory controller is further adapted for splitting the first process into at least two first sub-steps and for splitting the second process into at least two second sub-steps. The Flash memory controller is further adapted for executing the first and second sub-steps, and for interleaving execution of first and second sub-steps.

    摘要翻译： 闪存控制器通过第一闪存存储器接口耦合到第一闪存存储器封装，并通过第一闪存存储器接口耦合到第二闪存存储器封装。 闪存控制器被设计为接收与第一闪存存储器包相关的第一指令，并且根据第一指令执行第一处理。 闪存控制器还被设计为接收与第二闪存存储器包相关的第二指令，并且根据第二指令执行第二处理。 闪存控制器还适用于将第一进程分成至少两个第一子步骤，并将第二进程分成至少两个第二子步骤。 闪存控制器还适用于执行第一和第二子步骤，并且用于交错执行第一和第二子步骤。

    HAMMING RADIUS SEPARATED DEDUPLICATION LINKS
    46.
    发明申请
    HAMMING RADIUS SEPARATED DEDUPLICATION LINKS 审中-公开
    激活RADIUS分离的重复链接

    公开(公告)号：US20120210192A1

    公开(公告)日：2012-08-16

    申请号：US13453062

    申请日：2012-04-23

    申请人： Robert Haas ,  Nils Haustein ,  Craig Anthony Klein ,  Ulf Troppens ,  Daniel James Winarski

    发明人： Robert Haas ,  Nils Haustein ,  Craig Anthony Klein ,  Ulf Troppens ,  Daniel James Winarski

    IPC分类号： H03M13/19 ,  G06F11/10 ,  H03M13/29

    CPC分类号： G06F17/30286 ,  G06F3/0641 ,  H03M13/09

    摘要： A data storage system includes a data storage array configured for de-duplication of duplicate data therein by: identification of a plurality of portions of data; a comparison of each portion of the data to identify duplicate data and identification of a link associated with each duplicate data; a determination of whether a Hamming link-separation-distance of the identified link is greater than twice a Hamming radius of an error correction code in the data storage system; and replacement of the duplicate data with the identified link when it is determined that the Hamming link-separation-distance is greater than twice the Hamming radius.

    摘要翻译： 数据存储系统包括：数据存储阵列，其配置用于通过以下方式对重复数据删除重复数据：识别数据的多个部分; 数据的每个部分的比较以识别与每个重复数据相关联的重复数据和标识; 确定所识别的链路的汉明链路间隔距离是否大于数据存储系统中的纠错码的汉明半径的两倍; 并且当确定汉明链路间隔距离大于汉明半径的两倍时，用所识别的链路替换重复数据。

    SOLID-STATE STORAGE SYSTEM WITH PARALLEL ACCESS OF MULTIPLE FLASH/PCM DEVICES
    47.
    发明申请
    SOLID-STATE STORAGE SYSTEM WITH PARALLEL ACCESS OF MULTIPLE FLASH/PCM DEVICES 有权
    具有并行访问多个闪存/ PCM设备的固态存储系统

    公开(公告)号：US20110131472A1

    公开(公告)日：2011-06-02

    申请号：US12627364

    申请日：2009-11-30

    申请人： Theodore A. Antonakopoulos ,  Roy D. Cideciyan ,  Evangelos S. Eleftheriou ,  Robert Haas ,  Xiao-Yu Hu ,  Ilias Iliadis

    发明人： Theodore A. Antonakopoulos ,  Roy D. Cideciyan ,  Evangelos S. Eleftheriou ,  Robert Haas ,  Xiao-Yu Hu ,  Ilias Iliadis

    IPC分类号： H03M13/05 ,  G06F11/10 ,  H03M13/27

    CPC分类号： G06F11/1028 ,  G11C29/765

    摘要： Systems and methods are provided that confront the problem of failed storage integrated circuits (ICs) in a solid state drive (SSD) by using a fault-tolerant architecture along with one error correction code (ECC) mechanism for random/burst error corrections and an L-fold interleaving mechanism. The systems and methods described herein keep the SSD operational when one or more integrated circuits fail and allow the recovery of previously stored data from failed integrated circuits and allow random/burst errors to be corrected in other operational integrated circuits. These systems and methods replace the failed integrated circuits with fully functional/operational integrated circuits treated herein as spare integrated circuits. Furthermore, these systems and methods improve I/O performance in terms of maximum achievable read/write data rate.

    摘要翻译： 提供了通过使用容错架构以及用于随机/突发错误校正的一个纠错码（ECC）机制来解决固态驱动器（SSD）中的故障存储集成电路（IC）的问题的系统和方法，以及 L折叠交织机制。 当一个或多个集成电路出现故障并且允许从故障集成电路恢复先前存储的数据并且允许在其他操作集成电路中校正随机/突发错误时，本文描述的系统和方法保持SSD的可操作性。 这些系统和方法用作为备用集成电路处理的全功能/可操作集成电路来代替故障集成电路。 此外，这些系统和方法在最大可实现的读/写数据速率方面提高了I / O性能。

    Intra-disk coding scheme for data-storage systems
    48.
    发明授权
    Intra-disk coding scheme for data-storage systems 有权
    数据存储系统的磁盘内编码方案

    公开(公告)号：US07823011B2

    公开(公告)日：2010-10-26

    申请号：US11843323

    申请日：2007-08-22

    申请人： Ajay Dholakia ,  Ilias Iliadis ,  Robert Haas ,  Xiaoyu-Yu Hu ,  Evangelos S. Eleftheriou ,  Roman A. Pletka

    发明人： Ajay Dholakia ,  Ilias Iliadis ,  Robert Haas ,  Xiaoyu-Yu Hu ,  Evangelos S. Eleftheriou ,  Roman A. Pletka

    IPC分类号： G06F11/00

    CPC分类号： G06F11/1076 ,  G06F2211/1088

    摘要： Exemplary embodiments of the present invention comprise a method for the use of an intra-disk redundancy storage protection operation for the scrubbing of a disk. The method comprises initiating a disk scrubbing operation upon each disk of a plurality of disks that are comprised within a storage disk array, issuing a disk scrubbing command for a predetermined segment of the disks that are comprised within the storage disk array at a predetermined time interval, and identifying an unrecoverable segment on a disk. The method further comprises determining if unrecoverable sectors comprised within the unrecoverable segment can be reconstructed, and reconstructing the unrecoverable sectors of the unrecoverable segment and relocating the segment to a spare storage location on the disk in the event that the segment cannot be reconstructed within its original storage location.

    摘要翻译： 本发明的示例性实施例包括一种用于擦除盘的盘内冗余存储保护操作的方法。 该方法包括在包含在存储盘阵列内的多个盘的每个盘上启动磁盘擦除操作，以预定的时间间隔为包含在存储盘阵列内的盘的预定段发出磁盘擦除命令 并且识别磁盘上的不可恢复的段。 所述方法还包括确定是否可以重建包含在不可恢复的段内的不可恢复的扇区，以及在该段不能在其原始帧内重建的情况下，重构不可恢复段的不可恢复扇区并将该段重定位到盘上的备用存储位置 存储位置。

    Data path-based service deployment in hierarchical networks
    49.
    发明授权
    Data path-based service deployment in hierarchical networks 有权
    分层网络中基于数据路径的服务部署

    公开(公告)号：US07808896B2

    公开(公告)日：2010-10-05

    申请号：US10824665

    申请日：2004-04-14

    申请人： Robert Haas

    发明人： Robert Haas

    IPC分类号： H04J3/14 ,  H04L12/28 ,  H04J1/16

    CPC分类号： H04L45/125 ,  H04L45/04

    摘要： Provides optimizing a data path and forwarding a data from a start node to an end node over a network, wherein the data is forwarded through the data path which is determined by a data path option having a minimum overall capacity regarding first capacity values. Provides a first capacity value for a specific first node and for a specific first node function including determining a number of second data path options for the second nodes of the specific first node to perform the specific first node function, for each second data path option, the second nodes having one or more assigned second node functions. Provides a second capacity values for each of the second nodes and for each of the assigned second node functions, and determines overall capacity values of the nodes and for each of the assigned second node functions.

    摘要翻译： 提供优化数据路径并且通过网络将数据从起始节点转发到终端节点，其中数据通过由具有关于第一容量值的最小总容量的数据路径选项确定的数据路径转发。 为特定的第一节点和特定的第一节点功能提供第一容量值，包括为每个第二数据路径选项确定特定第一节点的第二节点的第二数据路径选项的数量以执行特定的第一节点功能， 所述第二节点具有一个或多个分配的第二节点功能。 为每个第二节点和每个分配的第二节点功能提供第二容量值，并且确定节点的总容量值以及针对每个分配的第二节点功能的总体容量值。

    Management of protocol information in PNNI hierarchical networks
    50.
    发明授权
    Management of protocol information in PNNI hierarchical networks 失效
    PNNI分层网络中协议信息的管理

    公开(公告)号：US07120119B2

    公开(公告)日：2006-10-10

    申请号：US09877479

    申请日：2001-06-08

    申请人： Laurent Frelechoux ,  Robert Haas ,  Michael Osborne

    发明人： Laurent Frelechoux ,  Robert Haas ,  Michael Osborne

    IPC分类号： G01R31/08

    CPC分类号： H04L45/04 ,  H04L45/02 ,  H04L45/026 ,  H04L45/64

    摘要： Methods and apparatus are provided for managing protocol information in a PNNI hierarchical network. In a PAR-enabled device (1) of the network, topology indicators (HC, LC) are assigned to protocol information encapsulated in PAR PTSEs received by the PAR-enabled device (1) from the network. The assignment of a topology indicator (HC, LC) to protocol information in a PAR PTSE is dependent on the location of the network node which originated that PAR PTSE in the PNNI topology as seen by the PAR-enabled device (1). Protocol information in received PAR PTSEs is then supplied to a protocol device (5) associated with the PAR-enabled device (1) in a manner dependent on the assigned topology indicators (HC, LC), for example with tags comprising the assigned topology indicators (HC, LC). The information supplied to the protocol device (5) thus reflects the topology indicators (HC, LC) which in turn reflect the location in the PNNI topology of the originating nodes of the PAR PTSEs. This allows the configuration of the network topology for the protocol in question to be controlled in dependence on the underlying PNNI topology.

    摘要翻译： 提供了用于管理PNNI分层网络中的协议信息的方法和装置。 在网络的启用PAR的设备（1）中，将拓扑指示符（HC，LC）分配给由PAR启用设备（1）从网络接收的PAR PTSE中封装的协议信息。 将拓扑指示符（HC，LC）分配给PAR PTSE中的协议信息取决于由PAR启用的设备（1）所见的在PNNI拓扑中产生PAR PTSE的网络节点的位置。 接收的PAR PTSE中的协议信息然后以取决于所分配的拓扑指示符（HC，LC）的方式提供给与启用PAR的设备（1）相关联的协议设备（5），例如使用包括所分配的拓扑指示符 （HC，LC）。 提供给协议设备（5）的信息因此反映了拓扑指示符（HC，LC），其又反映了PAR PTSE的始发节点的PNNI拓扑中的位置。 这允许根据潜在的PNNI拓扑来控制所讨论的协议的网络拓扑的配置。