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103 条记录 (耗时 0.041 秒)

    Systems and methods for reducing static and total power consumption
    44.
    发明授权
    Systems and methods for reducing static and total power consumption 失效
    降低静态和总功耗的系统和方法

    公开(公告)号：US08156355B2

    公开(公告)日：2012-04-10

    申请号：US12329051

    申请日：2008-12-05

    申请人： David Mendel ,  Vaughn Betz

    发明人： David Mendel ,  Vaughn Betz

    IPC分类号： G06F1/26 ,  G06F1/32

    CPC分类号： G06F1/32

    摘要： A method and system for reducing power consumption in a programmable logic device (PLD) is provided. The power consumption may be reduced by preferably continually considering power consumption as a factor in circuit design during the technology mapping, routing, and period following routing of the programmable logic device.

    摘要翻译： 提供了一种用于降低可编程逻辑器件（PLD）中功耗的方法和系统。 在可编程逻辑器件的技术映射，路由和后续周期期间，优选地可以连续地考虑功率消耗作为电路设计中的一个因素来降低功耗。

    Power-driven timing analysis and placement for programmable logic
    45.
    发明授权
    Power-driven timing analysis and placement for programmable logic 有权
    用于可编程逻辑的功率驱动时序分析和放置

    公开(公告)号：US08099692B1

    公开(公告)日：2012-01-17

    申请号：US12953764

    申请日：2010-11-24

    申请人： Yaron Kretchmer ,  Paul Leventis ,  Vaughn Betz

    发明人： Yaron Kretchmer ,  Paul Leventis ,  Vaughn Betz

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072 ,  Y02T10/82

    摘要： An integrated circuit is divided into two or more different regions, each region being a different voltage domain. In each of the regions, a voltage drop and its impact on performance will be quantified. A place and route engine (or another tool of a computer-aided design flow) will then take these timing considerations into account while performing partitioning of the device. A user's logic design is implemented into the logic array blocks taking into a voltage drop seen at those logic array blocks. Faster paths of the logic design are placed into faster logic array blocks, such as those in a core region of the integrated circuit.

    摘要翻译： 集成电路被分为两个或更多个不同的区域，每个区域是不同的电压域。 在每个区域，电压降及其对性能的影响将被量化。 然后，在执行设备分区时，会考虑到这些时间考虑因素，地方和路线引擎（或计算机辅助设计流程的另一个工具）将考虑这些时间考虑因素。 用户的逻辑设计被实现为在这些逻辑阵列块处看到的电压降的逻辑阵列块中。 将逻辑设计的更快的路径放置在更快的逻辑阵列块中，例如集成电路的核心区域中的那些。

    Techniques for grouping circuit elements into logic blocks
    47.
    发明授权
    Techniques for grouping circuit elements into logic blocks 失效
    将电路元件分组成逻辑块的技术

    公开(公告)号：US07707532B1

    公开(公告)日：2010-04-27

    申请号：US11844216

    申请日：2007-08-23

    申请人： Ketan Padalia ,  Kimberly Bozman ,  Vaughn Betz

    发明人： Ketan Padalia ,  Kimberly Bozman ,  Vaughn Betz

    IPC分类号： G06F17/50 ,  G06F9/45

    CPC分类号： G06F17/505 ,  G06F17/5072 ,  G06F17/5077 ,  Y02T10/82

    摘要： Techniques are provided for grouping circuits in a user design for a programmable integrated circuit into logic blocks. A packing tool separates each circuit element into individual abstract blocks and groups the abstract block into logic blocks. A determination is made whether placement information indicates that a design goal would be improved by rearranging at least a portion of the user design. The user design can be rearranged by moving one or more of the abstract blocks into different logic blocks than the ones they were previously grouped with. Circuit elements in the same logic block can be separated and placed into different logic blocks to improve routability of the user design and signal timing.

    摘要翻译： 提供了用于将可编程集成电路的用户设计中的电路分组成逻辑块的技术。 包装工具将每个电路元件分成单独的抽象块，并将抽象块分组成逻辑块。 确定放置信息是否指示通过重新排列用户设计的至少一部分来提高设计目标。 可以通过将抽象块中的一个或多个移动到与之前分组的逻辑块不同的逻辑块中来重新排列用户设计。 相同逻辑块中的电路元件可以分离并放置到不同的逻辑块中，以改善用户设计和信号时序的可布线性。

    Optimizing long-path and short-path timing and accounting for manufacturing and operating condition variability
    49.
    发明授权
    Optimizing long-path and short-path timing and accounting for manufacturing and operating condition variability 有权
    优化长途径和短路时间，并对制造和运行状况变化进行考虑

    公开(公告)号：US07290232B1

    公开(公告)日：2007-10-30

    申请号：US11002976

    申请日：2004-12-01

    申请人： Ryan Fung ,  Vaughn Betz

    发明人： Ryan Fung ,  Vaughn Betz

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031

    摘要： Logic designs are optimized to satisfy long-path and short-path timing constraints for multiple process/operating condition corners. A path-based compilation phase determines an implementation for logic design paths, in part, by monitoring a set of paths that are important from a timing perspective and evaluating the timing performance of the set of monitored paths at one or more timing corners. A timing-analysis-based compilation phase determines transformations for converting sets of timing values from one timing corner to another timing corner. The compilation phase transforms timing delay values from one timing corner to another to facilitate analysis of timing performance at different corners. Timing slack values produced by analysis are transformed to map them from one timing corner to another. The transformed timing slack values from multiple corners are amalgamated. The amalgamated timing slack values are used by a compilation phase (that potentially only understands a single corner) to optimize a logic design for multiple corners.

    摘要翻译： 优化逻辑设计，以满足多个过程/操作条件角的长途径和短路时序约束。 基于路径的编译阶段确定逻辑设计路径的实现，部分地通过监视从时序角度重要的一组路径并且评估一个或多个定时角上的一组被监控路径的定时性能。 基于时序分析的编译阶段确定将一组定时值从一个定时角转换到另一个时间角的转换。 编译阶段将时序延迟值从一个定时角转换到另一个定时角，以便于分析不同角落的时序性能。 通过分析产生的时间松弛值被转换，以将它们从一个时间点转到另一个时间点。 来自多个角落的转换后的时间松弛值是合并的。 合并的定时松弛值由编译阶段（可能只能理解单个角）使用，以优化多个角的逻辑设计。

    Techniques for grouping circuit elements into logic blocks
    50.
    发明授权
    Techniques for grouping circuit elements into logic blocks 有权
    将电路元件分组成逻辑块的技术

    公开(公告)号：US07275228B1

    公开(公告)日：2007-09-25

    申请号：US10716309

    申请日：2003-11-17

    申请人： Ketan Padalia ,  Kimberly Bozman ,  Vaughn Betz

    发明人： Ketan Padalia ,  Kimberly Bozman ,  Vaughn Betz

    IPC分类号： G06F9/45 ,  G06F17/50

    CPC分类号： G06F17/505 ,  G06F17/5072 ,  G06F17/5077 ,  Y02T10/82

    摘要： Techniques are provided for grouping circuits in a user design for a programmable integrated circuit into logic blocks. A packing tool separates each circuit element into individual abstract blocks and groups the abstract block into logic blocks. A determination is made whether placement information indicates that a design goal would be improved by rearranging at least a portion of the user design. The user design can be rearranged by moving one or more of the abstract blocks into different logic blocks than the ones they were previously grouped with. Circuit elements in the same logic block can be separated and placed into different logic blocks to improve routability of the user design and signal timing.

    摘要翻译： 提供了用于将可编程集成电路的用户设计中的电路分组成逻辑块的技术。 包装工具将每个电路元件分成单独的抽象块，并将抽象块分组成逻辑块。 确定放置信息是否指示通过重新排列用户设计的至少一部分来提高设计目标。 可以通过将抽象块中的一个或多个移动到与之前分组的逻辑块不同的逻辑块中来重新排列用户设计。 相同逻辑块中的电路元件可以分离并放置到不同的逻辑块中，以改善用户设计和信号时序的可布线性。