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公开(公告)号：US06405276B1
公开(公告)日：2002-06-11
申请号：US09210135
申请日：1998-12-10
IPC分类号： G06F1338
CPC分类号： G06F13/4059 , G06F13/4031
摘要： A bus bridge with a pool of buffers sets including first and second buffer sets. The bridge includes steering logic for directing transactions issued by a first peripheral device to the first buffer set and transactions issued by the second peripheral device to the second buffer set. The bus bridge is configured to pull posted memory write transactions ahead of a delayed read completion transaction in the first buffer set in response to identifying the first peripheral device as a target of a read request issued by a processor. In one embodiment, the bus bridge is further configured to receive first and second device select signals from the first and second peripheral devices respectively. In this embodiment, the device select signals indicate the target of the read request issued by the processor. The bridge is configured, in one embodiment, such that the pulling of posted memory write transactions in the first buffer set leaves transactions in all buffer sets other than the first buffer set unaffected in response to the read request. The invention further contemplates a computer system that includes a processor coupled to a system memory via a host bus and a bus bridge as described coupled between the host bus and a secondary bus. The bridge is most preferably configured such that transactions issued by the first peripheral device are stored in the first buffer set and transactions issued by the second peripheral device are stored in the second buffer set. In one embodiment, the device driver is designed to issue the load request in response to receiving an interrupt or to check status in the device. The source of the interrupt is preferably the target of the load request.
摘要翻译： 具有缓冲器集合的总线桥，包括第一和第二缓冲器组。 该桥包括用于将由第一外围设备发出的交易指向第一缓冲器组的转向逻辑，以及由第二外围设备向第二缓冲器组发出的事务。 总线桥被配置为响应于将第一外围设备识别为由处理器发出的读取请求的目标，在第一缓冲器集合中的延迟读取完成事务之前拉动已存储的写入事务。 在一个实施例中，总线桥还被配置为分别从第一和第二外围设备接收第一和第二设备选择信号。 在本实施例中，设备选择信号指示由处理器发出的读取请求的目标。 在一个实施例中，桥被配置为使得在第一缓冲器组中拉动已发布的存储器写入事务使得除了响应于读取请求不受影响的第一缓冲器集之外的所有缓冲器集中的事务。 本发明进一步设想一种计算机系统，其包括经由主机总线和总线桥连接到系统存储器的处理器，其耦合在主机总线和辅助总线之间。 该桥最优选地配置为使得由第一外围设备发出的交易存储在第一缓冲器组中，并且由第二外围设备发出的事务存储在第二缓冲器组中。 在一个实施例中，设备驱动器被设计为响应于接收到中断或检查设备中的状态而发出加载请求。 中断源最好是加载请求的目标。
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42.发明授权Method and system for supporting multiple local buses operating at different frequencies 失效支持多个本地总线工作在不同频率的方法和系统公开(公告)号：US06295568B1
公开(公告)日：2001-09-25
申请号：US09055414
申请日：1998-04-06
IPC分类号： G06F1338
CPC分类号： G06F13/4022
摘要： A method and system for supporting multiple Peripheral Component Interconnect (PCI) local buses through a single PCI host bridge having multiple PCI interfaces within a data-processing system are disclosed. In accordance with the method and system of the present invention, a processor and a system memory are connected to a system bus. One or more PCI local buses are connected to the system bus through a single PCI host bridge having bus and frequency control logic and bus clocks. The PCI local buses include sets of in-line electronic switches, dividing each PCI local bus into PCI local bus segments for supporting more PCI peripheral component slots then are called out by the PCI local bus standard. The sets of in-line electronic switches are open and closed in accordance with the bus and frequency control logic within the PCI host bridge thereby allowing the PCI peripheral component slots to operate at different bus frequencies, including bus frequencies higher than 66 MHz by using the bus clocks. The sets of in-line electronic switches further allowing different bus segments on the same PCI logical bus to dynamically be operated at different frequencies.
摘要翻译： 公开了一种通过在数据处理系统内具有多个PCI接口的单个PCI主机桥来支持多个外围组件互连（PCI）局部总线的方法和系统。 根据本发明的方法和系统，处理器和系统存储器连接到系统总线。 一个或多个PCI本地总线通过具有总线和频率控制逻辑和总线时钟的单个PCI主机桥连接到系统总线。 PCI本地总线包括一系列在线电子开关，将每个PCI本地总线划分为PCI本地总线段，以支持更多的PCI外设组件插槽，然后由PCI本地总线标准进行调用。 这些串联式电子开关根据PCI主机桥内的总线和频率控制逻辑开启和关闭，从而允许PCI外设组件插槽在不同的总线频率下工作，包括高于66MHz的总线频率，通过使用 总线时钟 这些在线电子开关进一步允许在同一PCI逻辑总线上的不同总线段动态地以不同的频率工作。
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43.发明授权Method and system for preventing peripheral component interconnect (PCI) peer-to-peer access across multiple PCI host bridges within a data processing system 失效用于防止在数据处理系统内的多个PCI主机桥的外围组件互连（PCI）对等访问的方法和系统
公开(公告)号：US5761461A
公开(公告)日：1998-06-02
申请号：US766735
申请日：1996-12-13
CPC分类号： G06F13/4027
摘要： A method for preventing peer-to-peer access across separate Peripheral Component Interconnect (PCI) host bridges within a data-processing system is described. In accordance with the method and system of the present invention, during an access request from a PCI device, a first determination is made as to whether or not the access request is for a system memory attached to a system bus. In response to a determination that the access request is not for a system memory attached to the system bus, another determination is made as to whether or not the access request is for a PCI device under the same PCI host bridge as the requesting PCI device. In response to a determination that the access request is not for a PCI device under the same PCI host bridge as the requesting PCI device, denying the access request such that a PCI peer-to-peer access across separate PCI host bridges within a data processing system is prevented.
摘要翻译： 描述了用于防止在数据处理系统内的分开的外围组件互连（PCI）主机桥的对等访问的方法。 根据本发明的方法和系统，在来自PCI设备的访问请求期间，首先确定访问请求是否用于连接到系统总线的系统存储器。 响应于确定访问请求不是连接到系统总线的系统存储器，则另外确定访问请求是否用于与请求的PCI设备相同的PCI主机桥下的PCI设备。 响应于确定访问请求不是针对与请求的PCI设备相同的PCI主机桥下的PCI设备，拒绝访问请求，使得跨数据处理中的单独PCI主机桥的PCI对等访问 系统被阻止。
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44.发明授权System and method for enhancement of system bus to mezzanine bus transactions 失效将系统总线增强到夹层总线交易的系统和方法
公开(公告)号：US5673399A
公开(公告)日：1997-09-30
申请号：US552034
申请日：1995-11-02
CPC分类号： G06F13/4027
摘要： A data processing system includes a host processor, a number of peripheral devices, and one or more bridges which may connect between the host, peripheral devices and other hosts or peripheral devices such as in a network. Each bridge, such as a PCI host bridge, connects between a primary bus (e.g system bus) and a secondary bus wherein for the purpose of clarity, the primary bus will be considered as the source for outbound transactions and the destination for inbound transactions and the secondary bus would be considered the destination for outbound transactions and the source for inbound transactions. The host bridge includes an outbound data path, an inbound data path, and a control mechanism. The outbound data path includes a queued buffer for storing transactions in order of receipt from the primary bus where the requests in the queued buffer may be mixed as between read requests and write transactions, the outbound path also includes a number of parallel buffers for storing read reply data and address information. The inbound path is a mirror image of the outbound path with read requests and write requests being stored in a sequential buffer and read replies being stored in a number of parallel buffers. Both the inbound path and the outbound path in the host bridge are controlled by a state machine which takes into consideration activity in both directions and permits or inhibits bypass transactions based on the protocol of the buses being interconnected through the bridge.
摘要翻译： 数据处理系统包括主处理器，多个外围设备以及可以在主机，外围设备和其他主机或诸如网络中的外围设备之间连接的一个或多个网桥。 每个桥梁（如PCI主机桥）连接在主总线（例如系统总线）和辅助总线之间，为了清楚起见，主总线将被视为出站事务的来源和入站事务的目的地， 辅助总线将被视为出站交易的目的地和入站交易的来源。 主桥包括出站数据路径，入站数据路径和控制机制。 出站数据路径包括排队缓冲器，用于按照从主总线接收的顺序存储事务，其中排队缓冲器中的请求可以在读请求和写事务之间混合，出站路径还包括多个用于存储读取的并行缓冲器 回复数据和地址信息。 入站路径是出站路径的镜像，读取请求和写入请求存储在顺序缓冲区中，并且读取回复存储在多个并行缓冲区中。 主桥中的入站路径和出站路径都由状态机控制，该状态机考虑到两个方向的活动，并且基于通过桥互连的总线的协议允许或禁止旁路交易。
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公开(公告)号：US07165110B2
公开(公告)日：2007-01-16
申请号：US09903725
申请日：2001-07-12
摘要： A system and method for establishing multiple connections using a private data field of a communication management protocol is provided. With the present invention, a Service ID identifies a specific consumer and the private data field contains a list of connection attributes for each connection that is to be established. An active side requests a connection and the passive side replies to the connection request. The active side sends the passive side a connection establishment request. This connection establishment request includes a Service ID which identifies a passive side process associated with a service. This connection establishment request also includes communication attributes of one or more connected services and datagram services associated with the Service ID. The passive passes the connection request to a process associated with the service. If the passive side process does not wish to carry out the service, a negative reply message is returned to the active side. If the passive side process does wish to carry out the service, a positive reply is returned to the active side and the reply includes the communication attributes for the connection and unreliable services associated with the Service ID used in the connection establishment request.
摘要翻译： 提供了一种使用通信管理协议的私有数据字段建立多个连接的系统和方法。 利用本发明，服务ID标识特定消费者，并且专用数据字段包含要建立的每个连接的连接属性的列表。 主动端请求连接，被动方回复连接请求。 主动端将被动方发送连接建立请求。 该连接建立请求包括识别与服务相关联的被动侧进程的服务ID。 该连接建立请求还包括与服务ID相关联的一个或多个连接的服务和数据报服务的通信属性。 被动将连接请求传递给与服务关联的进程。 如果被动侧进程不希望执行该服务，则将一个否定的回复消息返回到主动端。 如果被动侧进程确实希望执行该服务，则肯定的答复返回到主动侧，并且回复包括用于连接的通信属性和与在连接建立请求中使用的服务ID相关联的不可靠服务。
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公开(公告)号：US07149220B2
公开(公告)日：2006-12-12
申请号：US10132456
申请日：2002-04-25
IPC分类号： H04L12/56
CPC分类号： H04L29/06 , H04L49/90 , H04L69/326
摘要： A method, system, and product in a data processing system are disclosed for managing data transmitted from a first end node to a second end node included in the data processing system. A logical connection is established between the first end node and the second end node prior to transmitting data between the end nodes. An instance number is associated with this particular logical connection. The instance number is included in each packet transmitted between the end nodes while this logical connection remains established. The instance number remains constant during this logical connection. The instance number is altered, such as by incrementing it, each time a logical connection between these end nodes is reestablished. Thus, each packet is associated with a particular instance of the logical connection. When a packet is received, the instance number included in the packet may be used to determine whether the packet is a stale packet transmitted during a previous logical connection between these end nodes.
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公开(公告)号：US07116673B2
公开(公告)日：2006-10-03
申请号：US09925583
申请日：2001-08-09
CPC分类号： H04L61/1541 , H04L29/12113 , H04L49/90 , H04L69/16 , H04L69/168 , H04L69/22
摘要： A method for determining parameters needed to communicate with a remote node in a computer network is provided. The invention comprises determining the location of the remote node to which an InfiniBand (IB) node might desire to communicate. This resolution comprises determining the location of the remote node based on a desired application or service, and then determining the IB parameters needed to communicate with the remote node. The resolution might also involve determining the specific queue pairs that associated with the service dynamically. The general solution is applied to IP service resolution.
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公开(公告)号：US06760793B2
公开(公告)日：2004-07-06
申请号：US10207449
申请日：2002-07-29
IPC分类号： G06F302
CPC分类号： G06F13/385
摘要： A method and implementing computer system are provided which allows for significantly improved input/output (I/O) subsystem designs in all systems which include serialized I/O transactions such as so-called Express specification systems. Transaction control methodology is implemented to improve Express design requirements for Express devices such as an Express switch, Express-PCI bridge, endpoint, and root complex. This is accomplished by utilizing improved transaction ordering and state machine and corresponding buffer design and improved flow control credit methodology which enables improved processing for controlling transactions flowing through Express devices including Express switches and Express-PCI bridges. An Express-PCI/PCIX transition bridge design is also provided, along with the flow control credit methodology and implementation within the Express-PCI/PCIX bridge design to enable efficient interfacing between Express and legacy or existing PCI/PCIX systems.
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公开(公告)号：US06607125B1
公开(公告)日：2003-08-19
申请号：US09450985
申请日：1999-11-29
IPC分类号： G06K710
CPC分类号： G08B13/2414 , G06K7/10851 , G06K19/07758 , G08B13/2417 , G08B13/246 , G08B13/2482
摘要： An improved handheld merchandise scanning device and method are disclosed. A first and second mode are enabled in the scanning device for scanning a product tag which includes product information and a security tag. The product tag is scanned utilizing the scanning device in the first mode to obtain the product information without deactivating the security tag. The product tag is scanned utilizing the scanning device in the second mode to concurrently obtain the product information and deactivate the security tag.
摘要翻译： 公开了一种改进的手持商品扫描装置和方法。 在扫描装置中启用第一和第二模式以扫描包括产品信息和安全标签的产品标签。 使用第一模式中的扫描装置扫描产品标签，以获得产品信息而不停用安全标签。 使用第二模式的扫描装置扫描产品标签，以同时获取产品信息并停用安全标签。
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50.发明授权Driver/receiver circuitry for enhanced PCI bus with differential signaling 失效驱动器/接收器电路，用于具有差分信号的增强型PCI总线
公开(公告)号：US6070211A
公开(公告)日：2000-05-30
申请号：US872823
申请日：1997-06-11
CPC分类号： G06F13/4072
摘要： A system of supporting differential signalling circuitry in an enhanced PCI bus within a data processing system is disclosed The enhanced PCI bus comprises a plurality of differential signal conductor pairs. A system and method in accordance with the present invention comprises a system for providing each of the plurality of differential signal pairs over a first line and a second line, the first line having a front end and a back end, the second line having a front end and a back end. The system and method includes a differential driver for driving the first line and the second line with a small voltage change of equal amounts in opposite direction to change logic states, a receiver for sensing a voltage change between the first line and the second line and a termination network coupled to the first line and second line for terminating the first line and the second line. According to the system and method disclosed herein, the present invention provides for higher frequency capability and lower noise to signal ratio, thereby allowing the enhenced PCI bus to be compatible with a legacy PCI bus.
摘要翻译： 公开了一种在数据处理系统内的增强型PCI总线中支持差分信令电路的系统。增强型PCI总线包括多个差分信号导体对。 根据本发明的系统和方法包括用于在第一线和第二线上提供多个差分信号对中的每一个的系统，第一线具有前端和后端，第二线具有前端 结束和后端。 该系统和方法包括用于驱动第一线路和第二线路的差分驱动器，其具有相反方向上相等量的小的电压变化以改变逻辑状态，用于感测第一线路和第二线路之间的电压变化的接收机以及 耦合到第一线路的终端网络和用于终止第一线路和第二线路的第二线路。 根据本文公开的系统和方法，本发明提供了更高的频率能力和更低的噪声与信号比，从而允许增强的PCI总线与传统PCI总线兼容。
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