公开(公告)号：US06327197B1

公开(公告)日：2001-12-04

申请号：US09660534

申请日：2000-09-13

Applicant: Juhan Kim ,  Hing Wong

Inventor： Juhan Kim ,  Hing Wong

IPC: G11C700

CPC classification number: G11C29/808

Abstract: A memory architecture is disclosed that employs multiple column redundancies which provide multiple options for replacing a defective global odd or even bit line. Each column memory has two multiplexers, one for selecting a global odd bit line and another for selecting a global even bit line. Two or more column redundancies are coupled to each of the multiplexer in the column memory. In a first embodiment, the global odd and even bit lines are connected through odd and even sense amps in a regular column. In a second embodiment, the global odd bit line in a regular column connects through odd sense amps, while the global even bit line in the regular column connects through even sense amps. In a third embodiment, two or more sets of redundancy columns are commonly coupled to a left adjacent regular column and a right adjacent regular column.

Abstract translation: 公开了一种采用多列冗余的存储器架构，其提供用于替换有缺陷的全局奇数或偶数位线的多个选项。 每列存储器具有两个多路复用器，一个用于选择全局奇数位线，另一个用于选择全局偶数位线。 两列或更多列冗余被耦合到列存储器中的多路复用器中的每一个。 在第一实施例中，全局奇数和偶数位线通过常规列中的奇数和偶数感测放大器连接。 在第二实施例中，常规列中的全局奇数位线通过奇数检测放大器连接，而常规列中的全局偶数位线通过均匀感测放大器连接。 在第三实施例中，两组或多组冗余列通常耦合到左相邻规则列和右相邻常规列。

公开(公告)号：US06262928B1

公开(公告)日：2001-07-17

申请号：US09661165

申请日：2000-09-13

Applicant: Juhan Kim ,  Hing Wong

Inventor： Juhan Kim ,  Hing Wong

IPC: G11C2900

CPC classification number: G11C29/02 ,  G11C29/34

Abstract: The present invention discloses a parallel test circuit and method for testing even bit line and odd bit line in a memory block simultaneously. The parallel test circuit comprises an even test circuit for testing an even bit line and an odd test circuit for testing an odd bit line. The parallel test circuit also includes a write circuit for writing data to a bit line, a read circuit including a data sense amp, an output buffer, and a comparator. Furthermore, the present invention provides the capability to conduct disturbance test in neighboring even and odd cells.

Abstract translation: 本发明公开了一种用于同时测试存储块中偶数位线和奇数位线的并行测试电路和方法。 并联测试电路包括用于测试偶数位线的偶数测试电路和用于测试奇数位线的奇数测试电路。 并行测试电路还包括用于将数据写入位线的写入电路，包括数据读出放大器，输出缓冲器和比较器的读取电路。 此外，本发明提供了在相邻偶数和奇数单元中进行干扰测试的能力。

公开(公告)号：US6069815A

公开(公告)日：2000-05-30

申请号：US993538

申请日：1997-12-18

Applicant: Gerhard Mueller ,  Toshiaki Kirihata ,  Hing Wong

Inventor： Gerhard Mueller ,  Toshiaki Kirihata ,  Hing Wong

IPC: G11C11/401 ,  G11C7/18 ,  G11C8/14 ,  G11C16/06 ,  G11C5/06

CPC classification number: G11C7/18 ,  G11C8/14

Abstract: Disclosed is a semiconductor memory having a hierarchical bit line and/or word line architecture. In one embodiment, a memory having a hierarchical bit line architecture, particularly suitable for cells smaller than 8F.sup.2, includes a master bit line pair in each column, including first and second master bit lines with portions vertically spaced from one another. The first and second master bit lines twist with respect to one another in the vertical direction such that the first master bit line alternately overlies and underlies the second master bit line. A plurality of local bit line pairs in each column are coupled to memory cells, with at least one of the local bit lines coupled to a master bit line. In other embodiments, hierarchical word line configurations are disclosed including master word lines, sub-master word lines, and local word lines, electrically interconnected to one another via either switches, electrical contacts, or electrical circuits.

Abstract translation: 公开了具有分级位线和/或字线架构的半导体存储器。 在一个实施例中，具有特别适合于小于8F2的小区的分层位线架构的存储器包括每列中的主位线对，包括彼此垂直间隔开的部分的第一和第二主位线。 第一和第二主位线在垂直方向上相对于彼此扭曲，使得第一主位线交替地覆盖并位于第二主位线下方。 每列中的多个局部位线对耦合到存储器单元，其中至少一个局部位线耦合到主位线。 在其他实施例中，公开了分层字线配置，包括主字线，子主字线和本地字线，经由开关，电触点或电路彼此电互连。

公开(公告)号：US5903512A

公开(公告)日：1999-05-11

申请号：US923593

申请日：1997-09-04

Applicant: Hing Wong ,  Toshiaki Kirihata ,  Bozidar Krsnik

Inventor： Hing Wong ,  Toshiaki Kirihata ,  Bozidar Krsnik

IPC: G06F1/06 ,  G01R31/28 ,  G01R31/30 ,  G06F1/08 ,  G11C7/22 ,  G11C11/401 ,  G11C11/407 ,  G11C29/12 ,  G11C8/00

CPC classification number: G11C7/22 ,  G01R31/3016

Abstract: A circuit and method of using a test mode to control the timing of an internal signal using an external control in an integrated circuit. The test mode is designed such that the timing of the internal signal is derived from the external control which can be arbitrarily controlled by a tester. The external signal can be applied to an existing pin for chip control, provided that there is no conflict between the test mode and the operation of the integrated circuit.

Abstract translation: 使用测试模式来使用集成电路中的外部控制来控制内部信号的定时的电路和方法。 测试模式被设计为使得内部信号的定时来自外部控制，其可由测试仪任意控制。 外部信号可以应用于现有的针脚进行芯片控制，只要测试模式与集成电路的运行没有冲突。

公开(公告)号：US5559050A

公开(公告)日：1996-09-24

申请号：US269857

申请日：1994-06-30

Applicant: Johann Alsmeier ,  Wayne F. Ellis ,  Jack A. Mandelman ,  Hing Wong

Inventor： Johann Alsmeier ,  Wayne F. Ellis ,  Jack A. Mandelman ,  Hing Wong

IPC: H01L21/265 ,  H01L21/322 ,  H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/1095 ,  H01L27/0921 ,  H01L29/0642 ,  H01L29/1033 ,  H01L29/7838

Abstract: An anomalous threshold voltage dependence on channel width measured on 0.25 .mu.m ground rule generation trench-isolated buried-channel p-MOSFETs is used to enhance circuit performance. As the channel width is reduced, the magnitude of the threshold voltage first decreases before the onset of the expected sharp rise in V.sub.t for widths narrower than 0.4 .mu.m. Modeling shows that a "boron puddle" is created near the trench bounded edge as a result of transient enhanced diffusion (TED) during the gate oxidation step, which imposes a penalty on the off-current of narrow devices. TED is governed by interstitials produced by a deep phosphorus implant, used for latchup suppression, diffusing towards the trench sidewall and top surface of the device.

Abstract translation: 在0.25微米接地规则生成沟槽隔离埋沟p-MOSFET上测量的通道宽度的异常阈值电压依赖性用于增强电路性能。 随着沟道宽度的减小，阈值电压的幅度首先在宽度窄于0.4μm的Vt预期的急剧上升之前降低。 建模表明，在栅极氧化步骤期间，由于瞬态增强扩散（TED）的结果，在沟槽界限边缘附近产生“硼熔池”，这对狭窄器件的截止电流造成了惩罚。 TED由深磷植入物产生的间隙控制，用于闭锁抑制，向器件的沟槽侧壁和顶表面扩散。