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    SPIKE NEURAL NETWORK CIRCUIT INCLUDING SELF-CORRECTING CONTROL CIRCUIT AND METHOD OF OPERATION THEREOF
    42.
    发明申请
    SPIKE NEURAL NETWORK CIRCUIT INCLUDING SELF-CORRECTING CONTROL CIRCUIT AND METHOD OF OPERATION THEREOF 有权

    公开(公告)号：US20220253673A1

    公开(公告)日：2022-08-11

    申请号：US17538539

    申请日：2021-11-30

    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    Inventor： Kwang IL OH

    IPC: G06N3/04 ,  G06N3/063 ,  H03K3/354

    Abstract: Disclosed is a spike neural network circuit according to an embodiment of the present disclosure, which includes a self-correcting control circuit that generates an input signal and a first control code, a bias voltage generation circuit that generates a first bias voltage based on the first control code, a synaptic circuit including a first synaptic column that performs an operation of the input signal and a first weight signal and generates a first operation signal, a neuron circuit including a first neuron that generates a first output signal based on a comparison of the first operation signal and a threshold voltage, and a spike comparison circuit that generates a first comparison signal corresponding to a difference between the first output signal and a reference number, and the self-correcting control circuit further generates a second control code for correcting the first bias voltage.

    SPIKING NEURAL NETWORK CIRCUIT
    43.
    发明申请
    SPIKING NEURAL NETWORK CIRCUIT 有权

    公开(公告)号：US20220156556A1

    公开(公告)日：2022-05-19

    申请号：US17446685

    申请日：2021-09-01

    Applicant: Electronics and Telecommunications Research Institute

    Inventor： Kwang IL OH ,  Tae Wook KANG ,  Sung Eun KIM ,  Hyuk KIM ,  Hyung-IL PARK ,  Jae-Jin LEE

    IPC: G06N3/04 ,  G06N3/063 ,  H03K19/20

    Abstract: Disclosed is a spiking neural network circuit, which includes an axon circuit that generates an input spike signal, a first synapse zone and a second synapse zone each including one or more synapses, wherein each of the synapses is configured to perform an operation based on the input spike signal and each weight, and a neuron circuit that generates an output spike signal based on operation results of the synapses. The input spike signal is transferred to the first synapse zone and the second synapse zone through a tree structure, and each of branch nodes of the tree structure includes a driving buffer.

    SEMICONDUCTOR DEVICE INCLUDING CMOS CIRCUIT AND OPERATION METHOD THEREOF
    46.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING CMOS CIRCUIT AND OPERATION METHOD THEREOF 审中-公开

    公开(公告)号：US20190245532A1

    公开(公告)日：2019-08-08

    申请号：US16262738

    申请日：2019-01-30

    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    Inventor： Tae Wook KANG ,  Jae-Jin LEE ,  Kwang IL OH ,  Sung Eun KIM ,  Sukho LEE ,  Kyuseung HAN

    IPC: H03K17/14 ,  H03K17/08

    CPC classification number: H03K17/145 ,  H03K17/08 ,  H03K2017/0806 ,  H03K2217/0027

    Abstract: The inventive concept relates to a semiconductor device including a CMOS circuit and an operation method thereof. A semiconductor device according to an embodiment of the inventive concept includes a semiconductor circuit, a controller, and a voltage generator. The semiconductor circuit operates at a drive voltage to reduce the delay time between input and output as the temperature increases. The controller determines the malfunction of the CMOS circuit based on the difference between the source-drain current of the PMOS transistor and the source-drain current of the NMOS transistor as the temperature changes. The voltage generator generates or adjusts a body-bias voltage applied to the PMOS transistor or the NMOS transistor based on a malfunction determination of the controller. According to the inventive concept, malfunctions and performance deterioration occurring in a CMOS circuit operating at a low voltage may be reduced.

    NEUROMORPHIC ARITHMETIC DEVICE
    47.
    发明申请
    NEUROMORPHIC ARITHMETIC DEVICE 审中-公开

    公开(公告)号：US20180232635A1

    公开(公告)日：2018-08-16

    申请号：US15804912

    申请日：2017-11-06

    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

    Inventor： Kwang IL OH ,  Sung Eun KIM ,  Seong Mo PARK ,  Hyung-IL PARK ,  Jae-Jin LEE ,  Joo Hyun LEE

    IPC: G06N3/063 ,  G06F7/68 ,  G06F5/01

    CPC classification number: G06N3/0635 ,  G06F5/01 ,  G06F7/68 ,  H03K19/20

    Abstract: The present disclosure relates to a neuromorphic arithmetic device. The neuromorphic arithmetic device may include first and second synapse circuits, a charging/discharging circuit, a comparator, and a counter. The first synapse circuit may generate a first current by performing a first multiplication operation on a first PWM signal and a first weight, and the second synapse circuit may generate a second current by performing a second multiplication operation on a second PWM signal and a second weight. The charging/discharging circuit may store charges induced by the first current and the second current in a charging period, and may discharge the charges in a discharging period. The comparator may compare a voltage level of the charges discharged in the discharging period and a level of a reference voltage. The counter may count output pulses of an oscillator on the basis of a result of the comparison by the comparator.

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