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公开(公告)号：US08023324B2
公开(公告)日：2011-09-20
申请号：US12889461
申请日：2010-09-24
CPC分类号： G11C16/10 , G11C16/04 , G11C16/20 , G11C29/028 , G11C29/12005 , G11C29/50 , G11C29/50004 , G11C2029/5004
摘要： Self-calibration for a memory controller is performed by writing a voltage to a selected cell. Adjacent cells around the selected cell are programmed. After each of the adjacent programming operations, the voltage on the selected cell is read to determine any change in voltage caused by systemic offsets such as, for example, floating gate-to-floating gate coupling. These changes are averaged and stored in a table as an offset for use in adjusting a programming voltage or a read voltage in a particular area of memory represented by the offset. Self calibration method for temperature is determined by writing cells at different temperatures and reading at different temperatures to generate temperature offset tables for the write path and read path. These offset tables are used to adjust for systematic temperature related offsets during programming and during read.
摘要翻译： 通过向所选择的单元写入电压来执行存储器控制器的自校准。 对所选单元格周围的相邻单元进行编程。 在每个相邻的编程操作之后，读取所选择的单元上的电压，以确定由例如浮动栅极到浮置栅极耦合的系统偏移引起的任何电压变化。 这些变化被平均并存储在表中作为用于调整由偏移表示的存储器的特定区域中的编程电压或读取电压的偏移。 通过在不同温度下写入单元格并在不同温度读取来确定温度的自校准方法，以生成写入路径和读取路径的温度偏移表。 这些偏移表用于在编程期间和读取期间调整与系统温度相关的偏移。
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42.发明授权公开(公告)号：US08004887B2
公开(公告)日：2011-08-23
申请号：US12108105
申请日：2008-11-07
IPC分类号： G11C11/34
CPC分类号： G11C11/5621 , G11C5/066 , G11C7/1051 , G11C7/1057 , G11C7/1078 , G11C7/1084 , G11C7/16
摘要： Methods and memory devices are disclosed, for example a memory device that has both an analog path and a digital path that both share the same input/output pad. One of the two paths on each pad is selected in response to command signals that indicate the nature of the signal being either transmitted to the device or read from the device. Each digital path includes a latch for latching digital input data. Each analog path includes a sample/hold circuit for storing either analog data being read from or analog data being written to the memory device.
摘要翻译： 公开了方法和存储器件，例如具有共享相同输入/输出焊盘的模拟路径和数字路径两者的存储器件。 响应于指示信号的性质被传送到设备或从设备读取的命令信号来选择每个焊盘上的两个路径中的一个路径。 每个数字路径包括用于锁存数字输入数据的锁存器。 每个模拟路径包括采样/保持电路，用于存储被读取的模拟数据或被写入存储器件的模拟数据。
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43.发明授权Analog-to-digital and digital-to-analog conversion window adjustment based on reference cells in a memory device 有权基于存储器件中的参考单元的模数和数模转换窗口调整公开(公告)号：US07995412B2
公开(公告)日：2011-08-09
申请号：US11851649
申请日：2007-09-07
IPC分类号： G11C7/02
CPC分类号： G11C16/06 , G11C7/16 , G11C11/5621 , G11C16/0483 , G11C27/005 , G11C2211/5634
摘要： An analog-to-digital conversion window is defined by reference voltages stored in reference memory cells of a memory device. A first reference voltage is read to define an upper limit of the conversion window and a second reference voltage is read to define a lower limit of the conversion window. An analog voltage representing a digital bit pattern is read from a memory cell and converted to the digital bit pattern by an analog-to-digital conversion process using the conversion window as the limits for the sampling process. This scheme helps in real time tracking of the ADC window with changes in the program window of the memory array.
摘要翻译： 模数转换窗口由存储在存储器件的参考存储单元中的参考电压定义。 读取第一参考电压以限定转换窗口的上限，并且读取第二参考电压以定义转换窗口的下限。 表示数字位模式的模拟电压从存储单元读取，并通过使用转换窗口作为采样处理的限制的模数转换处理转换为数字位模式。 该方案通过存储器阵列的程序窗口的改变，有助于实时跟踪ADC窗口。
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公开(公告)号：US07957196B2
公开(公告)日：2011-06-07
申请号：US12829885
申请日：2010-07-02
IPC分类号： G11C16/06
CPC分类号： G11C16/0483 , G11C16/10 , G11C16/3454
摘要： Method of programming memory cells of series strings of memory cells include programming a target memory cell of a series string of memory cells after programming each memory cell of the string located between the target memory cell and a first end of the string, and verifying the programming of the target memory cell by applying a bias at a second end of the string opposite the first end and sensing a voltage developed at the first end in response to the bias.
摘要翻译： 编程存储器单元串的存储器单元的方法包括在对位于目标存储器单元和串的第一端之间的串的每个存储器单元进行编程之后对存储单元的串联串的目标存储器单元进行编程，以及验证编程 通过在与第一端相对的串的第二端处施加偏压并且响应于该偏压感测在第一端产生的电压来实现目标存储器单元。
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公开(公告)号：US20110128790A1
公开(公告)日：2011-06-02
申请号：US13025279
申请日：2011-02-11
IPC分类号： G11C16/04
CPC分类号： G11C16/28 , G11C11/5642 , G11C16/0483 , G11C27/005 , G11C27/02 , G11C2211/5621 , G11C2211/5634
摘要： A memory device that includes a sample and hold circuit coupled to a bit line. The sample and hold circuit stores a target threshold voltage for a selected memory cell. The memory cell is programmed and then verified with a ramped read voltage. The read voltage that turns on the memory cell is stored in the sample and hold circuit. The target threshold voltage is compared with the read voltage by a comparator circuit. When the read voltage is at least substantially equal to (i.e., is substantially equal to and/or starts to exceed) the target threshold voltage, the comparator circuit generates an inhibit signal.
摘要翻译： 一种存储器件，其包括耦合到位线的采样和保持电路。 采样和保持电路存储所选存储单元的目标阈值电压。 存储单元被编程，然后用斜坡读取电压进行验证。 将存储单元接通的读取电压存储在采样和保持电路中。 将目标阈值电压与比较器电路的读取电压进行比较。 当读取电压至少基本上等于（即，基本上等于和/或开始超过）目标阈值电压时，比较器电路产生禁止信号。
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公开(公告)号：US07898885B2
公开(公告)日：2011-03-01
申请号：US11879907
申请日：2007-07-19
IPC分类号： G11C7/02
CPC分类号： G11C16/28 , G11C11/5642 , G11C16/0483 , G11C27/005 , G11C27/02 , G11C2211/5621 , G11C2211/5634
摘要： A memory device that includes a sample and hold circuit coupled to a bit line. The sample and hold circuit stores a target threshold voltage for a selected memory cell. The memory cell is programmed and then verified with a ramped read voltage. The read voltage that turns on the memory cell is stored in the sample and hold circuit. The target threshold voltage is compared with the read voltage by a comparator circuit. When the read voltage is at least substantially equal to (i.e., is substantially equal to and/or starts to exceed) the target threshold voltage, the comparator circuit generates an inhibit signal.
摘要翻译： 一种存储器件，其包括耦合到位线的采样和保持电路。 采样和保持电路存储所选存储单元的目标阈值电压。 存储单元被编程，然后用斜坡读取电压进行验证。 将存储单元接通的读取电压存储在采样和保持电路中。 将目标阈值电压与比较电路的读取电压进行比较。 当读取电压至少基本上等于（即，基本上等于和/或开始超过）目标阈值电压时，比较器电路产生禁止信号。
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47.发明申请公开(公告)号：US20100122103A1
公开(公告)日：2010-05-13
申请号：US12108105
申请日：2008-11-07
CPC分类号： G11C11/5621 , G11C5/066 , G11C7/1051 , G11C7/1057 , G11C7/1078 , G11C7/1084 , G11C7/16
摘要： Methods and memory devices are disclosed, for example a memory device that has both an analog path and a digital path that both share the same input/output pad. One of the two paths on each pad is selected in response to command signals that indicate the nature of the signal being either transmitted to the device or read from the device. Each digital path includes a latch for latching digital input data. Each analog path includes a sample/hold circuit for storing either analog data being read from or analog data being written to the memory device.
摘要翻译： 公开了方法和存储器件，例如具有共享相同输入/输出焊盘的模拟路径和数字路径两者的存储器件。 响应于指示信号的性质被传送到设备或从设备读取的命令信号来选择每个焊盘上的两个路径中的一个路径。 每个数字路径包括用于锁存数字输入数据的锁存器。 每个模拟路径包括采样/保持电路，用于存储被读取的模拟数据或被写入存储器件的模拟数据。
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公开(公告)号：US07633798B2
公开(公告)日：2009-12-15
申请号：US11943916
申请日：2007-11-21
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C7/16 , G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/26 , G11C16/3418 , G11C16/3427 , G11C27/005 , G11C2211/5641
摘要： A memory device and programming and/or reading process is described that programs and/or reads the cells in the memory array with higher threshold voltage resolution than required. In programming non-volatile memory cells, this allows a more accurate threshold voltage placement during programming and enables pre-compensation for program disturb, increasing the accuracy of any subsequent read or verify operation on the cell. In reading/sensing memory cells, the increased threshold voltage resolution allows more accurate interpretations of the programmed state of the memory cell and also enables more effective use of probabilistic data encoding techniques such as convolutional code, partial response maximum likelihood (PRML), low-density parity check (LDPC), Turbo, and Trellis modulation encoding and/or decoding, reducing the overall error rate of the memory.
摘要翻译： 描述了存储器件和编程和/或读取过程，其以比所需的更高的阈值电压分辨率来编程和/或读取存储器阵列中的单元。 在编程非易失性存储器单元中，这允许在编程期间更准确的阈值电压放置，并且能够对程序干扰进行预补偿，从而提高单元上随后的任何读取或验证操作的准确性。 在读/读存储器单元中，增加的阈值电压分辨率允许更准确地解释存储器单元的编程状态，并且还能够更有效地使用概率数据编码技术，例如卷积码，部分响应最大似然（PRML） 密度奇偶校验（LDPC），Turbo和网格调制编码和/或解码，降低了存储器的总体错误率。
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公开(公告)号：US20090097318A1
公开(公告)日：2009-04-16
申请号：US11973677
申请日：2007-10-10
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/10 , G11C16/3454
摘要： An analog voltage NAND architecture non-volatile memory device and programming process is described that reduce the effects of NAND string resistance in source follower sensing by programming the cells in NAND memory cell strings to maintain the resistance presented by the unselected cells on the source-side of a given selected memory cell of the NAND string during both the verify and read. In particular, in one embodiment of the present invention, the cells in the NAND string are programmed sequentially in order from the cells closest the bit line to the final cell that is closest the source line in the string. This allows the source follower sensing of the verify and later read operations to read the programmed threshold voltage across the same stable source-side resistance 602, as the source-side unselected memory cells 20831-208N+1 will already have been programmed and thus will present the same channel resistance to both the source follower verify of the program operation and following source follower read operations, maintaining the compensation for the source-side resistance 602 of the source-side unselected memory cells 20831-208N+1.
摘要翻译： 描述了模拟电压NAND架构非易失性存储器件和编程过程，其通过对NAND存储器单元串中的单元进行编程来减少源极跟随器感测中的NAND串电阻的影响，以保持源极侧上未选择的单元所呈现的电阻 在验证和读取期间NAND串的给定选定存储单元。 特别地，在本发明的一个实施例中，NAND串中的单元按从最靠近位线的单元顺序顺序编程到最接近串中的源极线的最终单元。 这允许源跟随器检测验证和稍后读取操作以读取同一稳定源侧电阻602上的编程阈值电压，因为源侧未选择的存储器单元20831-208N + 1将已经被编程，因此将 对编程操作的源极跟随器验证和跟随源跟随器读取操作两者呈现相同的沟道电阻，保持源极侧未选择存储单元20831-208N + 1的源极侧电阻602的补偿。
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公开(公告)号：US20090067266A1
公开(公告)日：2009-03-12
申请号：US11851439
申请日：2007-09-07
CPC分类号： G11C16/10 , G11C16/04 , G11C16/20 , G11C29/028 , G11C29/12005 , G11C29/50 , G11C29/50004 , G11C2029/5004
摘要： Self-calibration for a memory controller is performed by writing a voltage to a selected cell. Adjacent cells around the selected cell are programmed. After each of the adjacent programming operations, the voltage on the selected cell is read to determine any change in voltage caused by systemic offsets such as, for example, floating gate-to-floating gate coupling. These changes are averaged and stored in a table as an offset for use in adjusting a programming voltage or a read voltage in a particular area of memory represented by the offset. Self calibration method for temperature is determined by writing cells at different temperatures and reading at different temperatures to generate temperature offset tables for the write path and read path. These offset tables are used to adjust for systematic temperature related offsets during programming and during read.
摘要翻译： 通过向所选择的单元写入电压来执行存储器控制器的自校准。 对所选单元格周围的相邻单元进行编程。 在每个相邻的编程操作之后，读取所选择的单元上的电压，以确定由例如浮动栅极到浮置栅极耦合的系统偏移引起的任何电压变化。 这些变化被平均并存储在表中作为用于调整由偏移表示的存储器的特定区域中的编程电压或读取电压的偏移。 通过在不同温度下写入单元格并在不同温度读取来确定温度的自校准方法，以生成写入路径和读取路径的温度偏移表。 这些偏移表用于在编程期间和读取期间调整与系统温度相关的偏移。
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