公开(公告)号：US10430163B2

公开(公告)日：2019-10-01

申请号：US15896301

申请日：2018-02-14

Applicant: Google LLC

Inventor： Jonathan Ross ,  Robert David Nuckolls ,  Christopher Aaron Clark ,  Chester Li ,  Gregory Michael Thorson

IPC: G06F7/78 ,  G06F7/76 ,  G11C7/10 ,  G11C8/04 ,  G11C19/28 ,  G06F7/00

Abstract: A circuit for transposing a matrix comprising reversal circuitry configured, for each of one or more diagonals of the matrix, to receive elements of the matrix in a first vector and generate a second vector that includes the elements of the matrix in an order that is a reverse of an order of the elements of the matrix in the first vector, and rotation circuitry configured, for each of the one or more diagonals of the matrix, to determine a number of positions by which to rotate the elements of the matrix in the second vector, receive the second vector of elements of the matrix, and generate a third vector that includes the elements of the matrix in the second vector in an order that is a rotation of the elements of the matrix in the second vector by the determined number of positions.

公开(公告)号：US10261786B2

公开(公告)日：2019-04-16

申请号：US15454214

申请日：2017-03-09

Applicant: Google LLC

Inventor： William Lacy ,  Gregory Michael Thorson ,  Christopher Aaron Clark ,  Norman Paul Jouppi ,  Thomas Norrie ,  Andrew Everett Phelps

IPC: G06F9/302 ,  G06F15/80 ,  G06F17/16 ,  G06F7/58 ,  G06N3/063 ,  G06F9/30 ,  G06F13/36 ,  G06F13/40 ,  G06F13/42

Abstract: A vector processing unit is described, and includes processor units that each include multiple processing resources. The processor units are each configured to perform arithmetic operations associated with vectorized computations. The vector processing unit includes a vector memory in data communication with each of the processor units and their respective processing resources. The vector memory includes memory banks configured to store data used by each of the processor units to perform the arithmetic operations. The processor units and the vector memory are tightly coupled within an area of the vector processing unit such that data communications are exchanged at a high bandwidth based on the placement of respective processor units relative to one another, and based on the placement of the vector memory relative to each processor unit.

公开(公告)号：US10192162B2

公开(公告)日：2019-01-29

申请号：US14845117

申请日：2015-09-03

Applicant: Google LLC

Inventor： Gregory Michael Thorson ,  Christopher Aaron Clark ,  Dan Luu

IPC: G06N3/08 ,  G06N5/04 ,  G06N3/063

Abstract: A circuit for performing neural network computations for a neural network comprising a plurality of layers, the circuit comprising: activation circuitry configured to receive a vector of accumulated values and configured to apply a function to each accumulated value to generate a vector of activation values; and normalization circuitry coupled to the activation circuitry and configured to generate a respective normalized value from each activation value.

公开(公告)号：US20190012294A1

公开(公告)日：2019-01-10

申请号：US16129663

申请日：2018-09-12

Applicant: Google LLC

Inventor： Gregory Michael Thorson ,  Andrew Everett Phelps ,  Olivier Temam

IPC: G06F15/80 ,  G06F9/30

Abstract: A vector reduction circuit configured to reduce an input vector of elements comprises a plurality of cells, wherein each of the plurality of cells other than a designated first cell that receives a designated first element of the input vector is configured to receive a particular element of the input vector, receive, from another of the one or more cells, a temporary reduction element, perform a reduction operation using the particular element and the temporary reduction element, and provide, as a new temporary reduction element, a result of performing the reduction operation using the particular element and the temporary reduction element. The vector reduction circuit also comprises an output circuit configured to provide, for output as a reduction of the input vector, a new temporary reduction element corresponding to a result of performing the reduction operation using a last element of the input vector.

公开(公告)号：US09952831B1

公开(公告)日：2018-04-24

申请号：US15614818

申请日：2017-06-06

Applicant: Google LLC

Inventor： Jonathan Ross ,  Robert David Nuckolls ,  Christopher Aaron Clark ,  Chester Li ,  Gregory Michael Thorson

IPC: G06F7/78 ,  G11C7/10 ,  G06F7/76 ,  G11C8/04 ,  G11C19/28

CPC classification number: G06F7/78 ,  G06F7/00 ,  G06F7/768 ,  G11C7/1012 ,  G11C8/04 ,  G11C19/28

Abstract: A circuit for transposing a matrix comprising reversal circuitry configured, for each of one or more diagonals of the matrix, to receive elements of the matrix in a first vector and generate a second vector that includes the elements of the matrix in an order that is a reverse of an order of the elements of the matrix in the first vector, and rotation circuitry configured, for each of the one or more diagonals of the matrix, to determine a number of positions by which to rotate the elements of the matrix in the second vector, receive the second vector of elements of the matrix, and generate a third vector that includes the elements of the matrix in the second vector in an order that is a rotation of the elements of the matrix in the second vector by the determined number of positions.

公开(公告)号：US20240211534A1

公开(公告)日：2024-06-27

申请号：US18241805

申请日：2023-09-01

Applicant: Google LLC

Inventor： Dong Hyuk Woo ,  Gregory Michael Thorson ,  Andrew Everett Phelps ,  Olivier Temam ,  Jonathan Ross ,  Christopher Aaron Clark

IPC: G06F17/16 ,  G06F7/76 ,  G06F9/30 ,  G06N3/063 ,  G06N3/084

CPC classification number: G06F17/16 ,  G06F7/76 ,  G06F9/30032 ,  G06F9/30036 ,  G06N3/063 ,  G06N3/084

Abstract: A circuit comprises an input register configured to receive an input vector of elements, a control register configured to receive a control vector of elements, wherein each element of the control vector corresponds to a respective element of the input vector, and wherein each element specifies a permutation of a corresponding element of the input vector, and a permute execution circuit configured to generate an output vector of elements corresponding to a permutation of the input vector. Generating each element of the output vector comprises accessing, at the input register, a particular element of the input vector, accessing, at the control register, a particular element of the control vector corresponding to the particular element of the input vector, and outputting the particular element of the input vector as an element at a particular position of the output vector that is selected based on the particular element of the control vector.

公开(公告)号：US20240168914A1

公开(公告)日：2024-05-23

申请号：US18429142

申请日：2024-01-31

Applicant: Google LLC

Inventor： Gregory Michael Thorson ,  Andrew Everett Phelps ,  Olivier Temam

IPC: G06F15/80 ,  G06F9/30 ,  G06F9/38 ,  G06F17/16

CPC classification number: G06F15/8053 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/3877 ,  G06F9/3897 ,  G06F17/16 ,  G06N3/084

Abstract: A vector reduction circuit configured to reduce an input vector of elements comprises a plurality of cells, wherein each of the plurality of cells other than a designated first cell that receives a designated first element of the input vector is configured to receive a particular element of the input vector, receive, from another of the one or more cells, a temporary reduction element, perform a reduction operation using the particular element and the temporary reduction element, and provide, as a new temporary reduction element, a result of performing the reduction operation using the particular element and the temporary reduction element. The vector reduction circuit also comprises an output circuit configured to provide, for output as a reduction of the input vector, a new temporary reduction element corresponding to a result of performing the reduction operation using a last element of the input vector.

公开(公告)号：US20230297372A1

公开(公告)日：2023-09-21

申请号：US18074990

申请日：2022-12-05

Applicant: Google LLC

Inventor： William Lacy ,  Gregory Michael Thorson ,  Christopher Aaron Clark ,  Norman Paul Jouppi ,  Thomas Norrie ,  Andrew Everett Phelps

IPC: G06F9/30 ,  G06F15/80 ,  G06F9/38 ,  G06F7/58 ,  G06F13/36 ,  G06F13/40 ,  G06F13/42 ,  G06F17/16

CPC classification number: G06F9/3001 ,  G06F7/588 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30098 ,  G06F9/3891 ,  G06F13/36 ,  G06F13/4068 ,  G06F13/4282 ,  G06F15/8053 ,  G06F15/8092 ,  G06F17/16 ,  G06F15/8046 ,  G06N3/063

Abstract: A vector processing unit is described, and includes processor units that each include multiple processing resources. The processor units are each configured to perform arithmetic operations associated with vectorized computations. The vector processing unit includes a vector memory in data communication with each of the processor units and their respective processing resources. The vector memory includes memory banks configured to store data used by each of the processor units to perform the arithmetic operations. The processor units and the vector memory are tightly coupled within an area of the vector processing unit such that data communications are exchanged at a high bandwidth based on the placement of respective processor units relative to one another, and based on the placement of the vector memory relative to each processor unit.

公开(公告)号：US11551138B2

公开(公告)日：2023-01-10

申请号：US16495815

申请日：2018-02-08

Applicant: GOOGLE LLC

Inventor： Ian Moray Mclaren ,  Norman Paul Jouppi ,  Clifford Hsiang Chao ,  Gregory Michael Thorson ,  Bjarke Hammersholt Roune

IPC: G06F15/173 ,  G06N20/00

Abstract: Methods, systems, and apparatus, including instructions encoded on storage media, for performing reduction of gradient vectors and similarly structured data that are generated in parallel, for example, on nodes organized in a mesh or torus topology defined by connections in at least two dimension between the nodes. The methods provide parallel computation and communication between nodes in the topology.

公开(公告)号：US20220172033A1

公开(公告)日：2022-06-02

申请号：US17520919

申请日：2021-11-08

Applicant: Google LLC

Inventor： Jonathan Ross ,  Gregory Michael Thorson

IPC: G06N3/063 ,  G06N5/04 ,  G06N3/08 ,  G06N3/04 ,  G06F15/80

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for computing a layer output for a convolutional neural network layer, the method comprising: receiving a plurality of activation inputs; forming a plurality of vector inputs from the plurality of activation inputs, each vector input comprising values from a distinct region within the multi-dimensional matrix; sending the plurality of vector inputs to one or more cells along a first dimension of the systolic array; generating a plurality of rotated kernel structures from each of the plurality of kernel; sending each kernel structure and each rotated kernel structure to one or more cells along a second dimension of the systolic array; causing the systolic array to generate an accumulated output based on the plurality of value inputs and the plurality of kernels; and generating the layer output from the accumulated output.