COMMAND LINE VOTING USING HASHING
    41.
    发明申请

    公开(公告)号:US20200142610A1

    公开(公告)日:2020-05-07

    申请号:US16179152

    申请日:2018-11-02

    Abstract: Systems and methods for command line voting are provided. Aspects include obtaining, by an output logic device, a plurality of memory blocks from a plurality of buffers, each of the plurality of memory blocks including two or more output commands generated from a processing circuit based on a sensor data input, generating, by a hash function, a hash value for each of the plurality of memory blocks, comparing the hash value for each of the plurality of memory blocks to determine an output memory block from the plurality of memory blocks, and outputting, to an output hardware, the two more output commands from the output memory block.

    Runtime reconfigurable dissimilar processing platform

    公开(公告)号:US10248430B2

    公开(公告)日:2019-04-02

    申请号:US15381918

    申请日:2016-12-16

    Abstract: One or more embodiments here relate to a processing platform for performing channel management and channel monitoring of a control channel. The processing platform includes a first microcontroller comprising a first core. The processing platform includes a second microcontroller comprising a second core. The second microcontroller is dissimilar to the first microcontroller. The first core is in an active state to perform the channel management of the control channel. The second core is in a monitor state to perform the channel monitoring of the control channel.

    RUNTIME RECONFIGURABLE DISSIMILAR PROCESSING PLATFORM

    公开(公告)号:US20180173537A1

    公开(公告)日:2018-06-21

    申请号:US15381918

    申请日:2016-12-16

    CPC classification number: G06F9/4405 G05D1/0077

    Abstract: One or more embodiments here relate to a processing platform for performing channel management and channel monitoring of a control channel. The processing platform includes a first microcontroller comprising a first core. The processing platform includes a second microcontroller comprising a second core. The second microcontroller is dissimilar to the first microcontroller. The first core is in an active state to perform the channel management of the control channel. The second core is in a monitor state to perform the channel monitoring of the control channel.

    Access key generation for computer-readable memory

    公开(公告)号:US09645948B2

    公开(公告)日:2017-05-09

    申请号:US14598430

    申请日:2015-01-16

    CPC classification number: G06F12/1466 G06F21/6218 G06F21/78 G06F2212/1052

    Abstract: In one example, a method includes receiving, by a controller device from a master device operably connected to the controller device, a memory access request configured to request access to computer-readable memory of the controller device. The method further includes sampling, by the controller device, time-varying data received from a controlled device operably connected to the controller device, and generating, by the controller device in response to receiving the memory access request, an access key using the sampled time-varying data received from the controlled device. The method further includes transmitting, by the controller device, the generated access key to the master device, and enabling, by the controller device, access to the computer-readable memory of the controller device in response to data write commands received from the master device that include an access code based on the access key.

    BACKUP CONTROL SYSTEM
    48.
    发明申请
    BACKUP CONTROL SYSTEM 审中-公开
    备份控制系统

    公开(公告)号:US20140303812A1

    公开(公告)日:2014-10-09

    申请号:US13857281

    申请日:2013-04-05

    CPC classification number: B64C13/505

    Abstract: An aircraft control system includes an effector module connected to a control input and a primary control module connected to the effector module. A microprocessor in the effector module provides a backup control path bypassing the primary control module when the primary control module is in a failed state.

    Abstract translation: 飞行器控制系统包括连接到控制输入的效应器模块和连接到效应器模块的主控制模块。 当主控制模块处于故障状态时,效应器模块中的微处理器提供绕过主控制模块的备用控制路径。

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