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公开(公告)号：US10768999B2
公开(公告)日：2020-09-08
申请号：US16031179
申请日：2018-07-10
Applicant: Hamilton Sundstrand Corporation
Inventor： Christopher Brian Noll , Steven A. Avritch
Abstract: Embodiments in include a system, a method, and a computer program product for performing intelligent load shedding for multi-channel processing system. The embodiments include a multi-channel processing system, wherein each channel of the multi-channel processing system includes a plurality of processors, and a plurality of links coupling each channel with each other channel in the multi-channel processing system, wherein the links are used to transmit status information of the plurality of processors. The embodiments also include a plurality of cooling elements coupled to each channel having the plurality of processors, wherein the plurality of cooling elements are configured to remove heat from the multi-channel processing system.
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公开(公告)号：US20200064824A1
公开(公告)日：2020-02-27
申请号：US16110192
申请日：2018-08-23
Applicant: Hamilton Sundstrand Corporation
Inventor： Steven A. Avritch , Christopher Brian Noll
Abstract: According to an aspect, a sever system includes a non-volatile storage device with a plurality of loadable configuration data and a configurable sever logic circuit configured responsive to a transfer of the loadable configuration data to perform a plurality of operations. The operations include mapping a plurality of module-level sever logic inputs to a plurality of module-specific sever logic functions as defined in the loadable configuration data. The module-level sever logic inputs are monitored by the configurable sever logic circuit based on the module-specific sever logic functions for a sever condition. A sever command to disconnect one or more outputs of a plurality of modules is triggered based on the module-specific sever logic functions and the module-level sever logic inputs.
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公开(公告)号：US10712736B2
公开(公告)日：2020-07-14
申请号：US16110192
申请日：2018-08-23
Applicant: Hamilton Sundstrand Corporation
Inventor： Steven A. Avritch , Christopher Brian Noll
Abstract: According to an aspect, a sever system includes a non-volatile storage device with a plurality of loadable configuration data and a configurable sever logic circuit configured responsive to a transfer of the loadable configuration data to perform a plurality of operations. The operations include mapping a plurality of module-level sever logic inputs to a plurality of module-specific sever logic functions as defined in the loadable configuration data. The module-level sever logic inputs are monitored by the configurable sever logic circuit based on the module-specific sever logic functions for a sever condition. A sever command to disconnect one or more outputs of a plurality of modules is triggered based on the module-specific sever logic functions and the module-level sever logic inputs.
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公开(公告)号：US20200065284A1
公开(公告)日：2020-02-27
申请号：US16112244
申请日：2018-08-24
Applicant: Hamilton Sundstrand Corporation
Inventor： Christopher Brian Noll , Steven A. Avritch
IPC: G06F13/40
Abstract: A system includes a computing system and a cable connector. The computing system includes a plurality of processors and an interconnect circuit configured to connect the plurality of processors to each other. The cable connector is configured to connect to the interconnect circuit and provide a channel identifier to the computing system, and the interconnect circuit is configured to set one of the plurality of processors as a system controller based on the channel identifier.
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公开(公告)号：US20200019446A1
公开(公告)日：2020-01-16
申请号：US16031179
申请日：2018-07-10
Applicant: Hamilton Sundstrand Corporation
Inventor： Christopher Brian Noll , Steven A. Avritch
Abstract: Embodiments in include a system, a method, and a computer program product for performing intelligent load shedding for multi-channel processing system. The embodiments include a multi-channel processing system, wherein each channel of the multi-channel processing system includes a plurality of processors, and a plurality of links coupling each channel with each other channel in the multi-channel processing system, wherein the links are used to transmit status information of the plurality of processors. The embodiments also include a plurality of cooling elements coupled to each channel having the plurality of processors, wherein the plurality of cooling elements are configured to remove heat from the multi-channel processing system.
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Patent Agency Ranking
公开(公告)号：US12154642B2
公开(公告)日：2024-11-26
申请号：US17500053
申请日：2021-10-13
Applicant: Hamilton Sundstrand Corporation
Inventor： Christopher Brian Noll
Abstract: Examples described herein provide a method for testing a memory associated with a processing system of an aircraft. The method includes performing, during operation of the processing system, an operational built-in test on the memory. The method further includes, responsive to detecting an error in the memory during the operational built-in test, performing a focused memory test at a location in the memory of the error. The method further includes, responsive the error being confirmed by the focused memory test, causing the processing system to be taken offline.
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公开(公告)号：US11100025B2
公开(公告)日：2021-08-24
申请号：US16112244
申请日：2018-08-24
Applicant: Hamilton Sundstrand Corporation
Inventor： Christopher Brian Noll , Steven A. Avritch
Abstract: A system includes a computing system and a cable connector. The computing system includes a plurality of processors and an interconnect circuit configured to connect the plurality of processors to each other. The cable connector is configured to connect to the interconnect circuit and provide a channel identifier to the computing system, and the interconnect circuit is configured to set one of the plurality of processors as a system controller based on the channel identifier.
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公开(公告)号：US10785073B1
公开(公告)日：2020-09-22
申请号：US16443078
申请日：2019-06-17
Applicant: Hamilton Sundstrand Corporation
IPC: H03K7/08 , H04L25/49 , G05B19/05 , G06F7/575 , G05B19/045
Abstract: A pulse width modulation signaling system includes a first control channel that is configured to receive a hardware Boolean command input from a first hardware status monitor, receive a software multi-bit command input from a first software system, and generate a first pulse width modulated signal that is representative of the Boolean command input and the software multi-bit command input. The hardware Boolean command input is a binary value of either a first state or a second state, the software multi-bit command input includes a binary value of either a first state or a second state, and the first pulse width modulated signal defines a duty cycle.
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公开(公告)号：US20230110926A1
公开(公告)日：2023-04-13
申请号：US17500053
申请日：2021-10-13
Applicant: Hamilton Sundstrand Corporation
Inventor： Christopher Brian Noll
Abstract: Examples described herein provide a method for testing a memory associated with a processing system of an aircraft. The method includes performing, during operation of the processing system, an operational built-in test on the memory. The method further includes, responsive to detecting an error in the memory during the operational built-in test, performing a focused memory test at a location in the memory of the error. The method further includes, responsive the error being confirmed by the focused memory test, causing the processing system to be taken offline.
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公开(公告)号：US10831383B2
公开(公告)日：2020-11-10
申请号：US16179152
申请日：2018-11-02
Applicant: HAMILTON SUNDSTRAND CORPORATION
Inventor： Christopher Brian Noll , Steven A. Avritch
Abstract: Systems and methods for command line voting are provided. Aspects include obtaining, by an output logic device, a plurality of memory blocks from a plurality of buffers, each of the plurality of memory blocks including two or more output commands generated from a processing circuit based on a sensor data input, generating, by a hash function, a hash value for each of the plurality of memory blocks, comparing the hash value for each of the plurality of memory blocks to determine an output memory block from the plurality of memory blocks, and outputting, to an output hardware, the two more output commands from the output memory block.
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