公开(公告)号：US20100110760A1

公开(公告)日：2010-05-06

申请号：US12390728

申请日：2009-02-23

申请人： Yiran Chen ,  Hai Li ,  Wenzhong Zhu ,  Xiaobin Wang ,  Henry Huang ,  Hongyue Liu

发明人： Yiran Chen ,  Hai Li ,  Wenzhong Zhu ,  Xiaobin Wang ,  Henry Huang ,  Hongyue Liu

IPC分类号： G11C11/00 ,  G11C11/416 ,  G11C7/00 ,  G11C11/24

CPC分类号： G11C13/004 ,  G11C11/1673 ,  G11C27/02 ,  G11C2013/0057 ,  G11C2207/2254

摘要： Resistive memory calibration for self-reference read methods are described. One method of self-reference reading a resistive memory unit includes setting a plurality of resistive memory units to a first resistive data state. The resistive memory units forms a memory array. Reading a sensed resistive data state for each resistive memory unit by applying a first read current and a second read current through each resistive memory unit and then comparing voltages formed by the first read current and the second read current to determine the sensed resistive data state for each resistive memory unit. Then the method includes adjusting the first or the second read current, read voltages, or storage device capacitance for each resistive memory unit where the sensed resistive data state was not the same as the first resistive data state until the sensed resistive data state is the same as the first resistive data state.

摘要翻译： 描述了自参考读取方法的电阻记忆校准。 读取电阻性存储器单元的一种自参考方法包括将多个电阻存储器单元设置为第一电阻数据状态。 电阻存储器单元形成存储器阵列。 通过施加第一读取电流和第二读取电流通过每个电阻性存储器单元，然后比较由第一读取电流和第二读取电流形成的电压，来为每个电阻性存储器单元读取感测的电阻数据状态，以确定感测的电阻数据状态 每个电阻存储器单元。 然后，该方法包括调整每个电阻性存储器单元的第一或第二读取电流，读取电压或存储器件电容，其中感测的电阻数据状态与第一电阻数据状态不同，直到感测的电阻数据状态相同 作为第一电阻数据状态。

公开(公告)号：US08213215B2

公开(公告)日：2012-07-03

申请号：US13015085

申请日：2011-01-27

申请人： Yiran Chen ,  Hai Li ,  Wenzhong Zhu ,  Xiaobin Wang ,  Henry Huang ,  Hongyue Liu

发明人： Yiran Chen ,  Hai Li ,  Wenzhong Zhu ,  Xiaobin Wang ,  Henry Huang ,  Hongyue Liu

IPC分类号： G11C11/00 ,  G11C5/14 ,  G11C7/06

CPC分类号： G11C13/004 ,  G11C11/1673 ,  G11C27/02 ,  G11C2013/0057 ,  G11C2207/2254

摘要： Resistive memory calibration for self-reference read methods are described. One method of self-reference reading a resistive memory unit includes setting a plurality of resistive memory units to a first resistive data state. The resistive memory units forms a memory array. Reading a sensed resistive data state for each resistive memory unit by applying a first read current and a second read current through each resistive memory unit and then comparing voltages formed by the first read current and the second read current to determine the sensed resistive data state for each resistive memory unit. Then the method includes adjusting the first or the second read current, read voltages, or storage device capacitance for each resistive memory unit where the sensed resistive data state was not the same as the first resistive data state until the sensed resistive data state is the same as the first resistive data state.

摘要翻译： 描述了自参考读取方法的电阻记忆校准。 读取电阻性存储器单元的一种自参考方法包括将多个电阻存储器单元设置为第一电阻数据状态。 电阻存储器单元形成存储器阵列。 通过施加第一读取电流和第二读取电流通过每个电阻性存储器单元，然后比较由第一读取电流和第二读取电流形成的电压，来为每个电阻性存储器单元读取感测的电阻数据状态，以确定感测的电阻数据状态 每个电阻存储器单元。 然后，该方法包括调整每个电阻性存储器单元的第一或第二读取电流，读取电压或存储器件电容，其中感测的电阻数据状态与第一电阻数据状态不同，直到感测的电阻数据状态相同 作为第一电阻数据状态。

公开(公告)号：US08199563B2

公开(公告)日：2012-06-12

申请号：US13149136

申请日：2011-05-31

申请人： Yiran Chen ,  Hai Li ,  Hongyue Liu ,  Yong Lu ,  Yang Li

发明人： Yiran Chen ,  Hai Li ,  Hongyue Liu ,  Yong Lu ,  Yang Li

IPC分类号： G11C11/00

CPC分类号： G11C11/1657 ,  G11C11/1659 ,  G11C11/1675 ,  Y10S977/935

摘要： A transmission gate-based spin-transfer torque memory unit is described. The memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. A NMOS transistor is in parallel electrical connection with a PMOS transistor and they are electrically connected with the source line and the magnetic tunnel junction data cell. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell. The PMOS transistor and the NMOS transistor are separately addressable so that a first write current in a first direction flows through the PMOS transistor and a second write current in a second direction flows through the NMOS transistor.

摘要翻译： 描述基于传输门的自旋转移转矩存储单元。 存储单元包括电耦合到位线和源极线的磁性隧道结数据单元。 NMOS晶体管与PMOS晶体管并联电连接，并且它们与源极线和磁性隧道结数据单元电连接。 磁隧道结数据单元被配置为通过使极化写入电流通过磁性隧道结数据单元在高电阻状态和低电阻状态之间切换。 PMOS晶体管和NMOS晶体管可单独寻址，使得第一方向上的第一写入电流流过PMOS晶体管，并且第二方向的第二写入电流流过NMOS晶体管。

公开(公告)号：US08098516B2

公开(公告)日：2012-01-17

申请号：US12855896

申请日：2010-08-13

申请人： Hai Li ,  Yiran Chen ,  Hongyue Liu ,  Xuguang Wang

发明人： Hai Li ,  Yiran Chen ,  Hongyue Liu ,  Xuguang Wang

IPC分类号： G11C11/00

CPC分类号： G11C11/1675 ,  G11C11/1659

摘要： A memory array includes a plurality of magnetic tunnel junction cells arranged in a 2 by 2 array. Each magnetic tunnel junction cell is electrically coupled between a bit line and a source line and each magnetic tunnel junction cell electrically coupled to a transistor. Each magnetic tunnel junction cell is configured to switch between a high resistance state and a low resistance state by passing a write current passing though the magnetic tunnel junction cell. A first word line is electrically coupled to a gate of first set of two of the transistors and a second word line is electrically coupled to a gate of a second set of two of the transistors. The source line is a common source line for the plurality of magnetic tunnel junctions.

摘要翻译： 存储器阵列包括以2×2阵列排列的多个磁性隧道结单元。 每个磁性隧道结单元电耦合在位线和源极线之间，并且每个磁性隧道结单元电耦合到晶体管。 每个磁性隧道结单元被配置为通过使经过磁性隧道结单元的写入电流通过高电阻状态和低电阻状态之间切换。 第一字线电耦合到第一组晶体管的第一组的栅极，并且第二字线电耦合到第二组二个晶体管的栅极。 源极线是用于多个磁性隧道结的公共源极线。

公开(公告)号：US20110228598A1

公开(公告)日：2011-09-22

申请号：US13149136

申请日：2011-05-31

申请人： Yiran Chen ,  Hai Li ,  Hongyue Liu ,  Yong Lu ,  Yang Li

发明人： Yiran Chen ,  Hai Li ,  Hongyue Liu ,  Yong Lu ,  Yang Li

IPC分类号： G11C11/14

CPC分类号： G11C11/1657 ,  G11C11/1659 ,  G11C11/1675 ,  Y10S977/935

摘要： A transmission gate-based spin-transfer torque memory unit is described. The memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. A NMOS transistor is in parallel electrical connection with a PMOS transistor and they are electrically connected with the source line and the magnetic tunnel junction data cell. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell. The PMOS transistor and the NMOS transistor are separately addressable so that a first write current in a first direction flows through the PMOS transistor and a second write current in a second direction flows through the NMOS transistor.

摘要翻译： 描述基于传输门的自旋转移转矩存储单元。 存储单元包括电耦合到位线和源极线的磁性隧道结数据单元。 NMOS晶体管与PMOS晶体管并联电连接，并且它们与源极线和磁性隧道结数据单元电连接。 磁隧道结数据单元被配置为通过使极化写入电流通过磁性隧道结数据单元在高电阻状态和低电阻状态之间切换。 PMOS晶体管和NMOS晶体管可单独寻址，使得第一方向上的第一写入电流流过PMOS晶体管，并且第二方向的第二写入电流流过NMOS晶体管。

公开(公告)号：US07974119B2

公开(公告)日：2011-07-05

申请号：US12170549

申请日：2008-07-10

申请人： Yiran Chen ,  Hai Li ,  Hongyue Liu ,  Yong Lu ,  Yang Li

发明人： Yiran Chen ,  Hai Li ,  Hongyue Liu ,  Yong Lu ,  Yang Li

IPC分类号： G11C11/00

CPC分类号： G11C11/1657 ,  G11C11/1659 ,  G11C11/1675 ,  Y10S977/935

摘要： A transmission gate-based spin-transfer torque memory unit is described. The memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. A NMOS transistor is in parallel electrical connection with a PMOS transistor and they are electrically connected with the source line and the magnetic tunnel junction data cell. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell. The PMOS transistor and the NMOS transistor are separately addressable so that a first write current in a first direction flows through the PMOS transistor and a second write current in a second direction flows through the NMOS transistor.

摘要翻译： 描述基于传输门的自旋转移转矩存储单元。 存储单元包括电耦合到位线和源极线的磁性隧道结数据单元。 NMOS晶体管与PMOS晶体管并联电连接，并且它们与源极线和磁性隧道结数据单元电连接。 磁隧道结数据单元被配置为通过使极化写入电流通过磁性隧道结数据单元在高电阻状态和低电阻状态之间切换。 PMOS晶体管和NMOS晶体管可单独寻址，使得第一方向上的第一写入电流流过PMOS晶体管，并且第二方向的第二写入电流流过NMOS晶体管。

公开(公告)号：US20110122679A1

公开(公告)日：2011-05-26

申请号：US13015085

申请日：2011-01-27

申请人： Yiran Chen ,  Hai Li ,  Wenzhong Zhu ,  Xiaobin Wang ,  Henry Huang ,  Hongyue Liu

发明人： Yiran Chen ,  Hai Li ,  Wenzhong Zhu ,  Xiaobin Wang ,  Henry Huang ,  Hongyue Liu

IPC分类号： G11C11/00

CPC分类号： G11C13/004 ,  G11C11/1673 ,  G11C27/02 ,  G11C2013/0057 ,  G11C2207/2254

摘要： Resistive memory calibration for self-reference read methods are described. One method of self-reference reading a resistive memory unit includes setting a plurality of resistive memory units to a first resistive data state. The resistive memory units forms a memory array. Reading a sensed resistive data state for each resistive memory unit by applying a first read current and a second read current through each resistive memory unit and then comparing voltages formed by the first read current and the second read current to determine the sensed resistive data state for each resistive memory unit. Then the method includes adjusting the first or the second read current, read voltages, or storage device capacitance for each resistive memory unit where the sensed resistive data state was not the same as the first resistive data state until the sensed resistive data state is the same as the first resistive data state.

摘要翻译： 描述了自参考读取方法的电阻记忆校准。 读取电阻性存储器单元的一种自参考方法包括将多个电阻存储器单元设置为第一电阻数据状态。 电阻存储器单元形成存储器阵列。 通过施加第一读取电流和第二读取电流通过每个电阻性存储器单元，然后比较由第一读取电流和第二读取电流形成的电压，来为每个电阻式存储器单元读取感测的电阻数据状态，以确定感测的电阻数据状态 每个电阻存储器单元。 然后，该方法包括调整每个电阻性存储器单元的第一或第二读取电流，读取电压或存储器件电容，其中感测的电阻数据状态与第一电阻数据状态不同，直到感测的电阻数据状态相同 作为第一电阻数据状态。

公开(公告)号：US07898838B2

公开(公告)日：2011-03-01

申请号：US12390728

申请日：2009-02-23

申请人： Yiran Chen ,  Hai Li ,  Wenzhong Zhu ,  Xiaobin Wang ,  Henry Huang ,  Hongyue Liu

发明人： Yiran Chen ,  Hai Li ,  Wenzhong Zhu ,  Xiaobin Wang ,  Henry Huang ,  Hongyue Liu

IPC分类号： G11C11/00 ,  G11C7/06 ,  G11C5/14

CPC分类号： G11C13/004 ,  G11C11/1673 ,  G11C27/02 ,  G11C2013/0057 ,  G11C2207/2254

摘要： Resistive memory calibration for self-reference read methods are described. One method of self-reference reading a resistive memory unit includes setting a plurality of resistive memory units to a first resistive data state. The resistive memory units forms a memory array. Reading a sensed resistive data state for each resistive memory unit by applying a first read current and a second read current through each resistive memory unit and then comparing voltages formed by the first read current and the second read current to determine the sensed resistive data state for each resistive memory unit. Then the method includes adjusting the first or the second read current, read voltages, or storage device capacitance for each resistive memory unit where the sensed resistive data state was not the same as the first resistive data state until the sensed resistive data state is the same as the first resistive data state.

摘要翻译： 描述了自参考读取方法的电阻记忆校准。 读取电阻性存储器单元的一种自参考方法包括将多个电阻存储器单元设置为第一电阻数据状态。 电阻存储器单元形成存储器阵列。 通过施加第一读取电流和第二读取电流通过每个电阻性存储器单元，然后比较由第一读取电流和第二读取电流形成的电压，来为每个电阻性存储器单元读取感测的电阻数据状态，以确定感测的电阻数据状态 每个电阻存储器单元。 然后，该方法包括调整每个电阻性存储器单元的第一或第二读取电流，读取电压或存储器件电容，其中感测的电阻数据状态与第一电阻数据状态不同，直到感测的电阻数据状态相同 作为第一电阻数据状态。

公开(公告)号：US20100095050A1

公开(公告)日：2010-04-15

申请号：US12252170

申请日：2008-10-15

申请人： Yiran Chen ,  Daniel S. Reed ,  Yong Lu ,  Hongyue Liu ,  Hai Li

发明人： Yiran Chen ,  Daniel S. Reed ,  Yong Lu ,  Hongyue Liu ,  Hai Li

IPC分类号： G06F12/02

CPC分类号： G11C7/24 ,  G11C5/143 ,  G11C11/16 ,  G11C13/0002

摘要： Method and apparatus for operating a memory device with a status register. In some embodiments, the memory device has a plurality of individually programmable non-volatile memory cells comprised of at least a resistive sense memory. The memory device engages an interface and maintains a status register in some embodiments by logging at least an error or busy signal during data transfer operations.

摘要翻译： 用于操作具有状态寄存器的存储器件的方法和装置。 在一些实施例中，存储器件具有由至少电阻式感测存储器组成的多个单独可编程的非易失性存储器单元。 在一些实施例中，存储器装置接合接口并维持状态寄存器，在数据传输操作期间至少记录错误或忙信号。

公开(公告)号：US20100080053A1

公开(公告)日：2010-04-01

申请号：US12242331

申请日：2008-09-30

申请人： Hai Li ,  Yiran Chen ,  Hongyue Liu ,  Xuguang Wang

发明人： Hai Li ,  Yiran Chen ,  Hongyue Liu ,  Xuguang Wang

IPC分类号： G11C11/02 ,  G11C11/409

CPC分类号： G11C11/1675 ,  G11C11/1659

摘要： The present disclosure relates to a memory array including a plurality of magnetic tunnel junction cells arranged in an array. Each magnetic tunnel junction cell is electrically coupled between a bit line and a source line. The magnetic tunnel junction cell is configured to switch between a high resistance state and a low resistance state by passing a write current passing though the magnetic tunnel junction cell. A transistor is electrically between the magnetic tunnel junction cell and the source line. A word line is electrically coupled to a gate of the transistor. The source line is a common source line for the plurality of magnetic tunnel junctions.

摘要翻译： 本公开涉及包括以阵列布置的多个磁性隧道结单元的存储器阵列。 每个磁性隧道结单元电连接在位线和源极线之间。 磁性隧道结单元通过使通过磁性隧道结单元的写入电流通过而在高电阻状态和低电阻状态之间切换。 晶体管电连接在磁性隧道结电池和源极线之间。 字线电耦合到晶体管的栅极。 源极线是用于多个磁性隧道结的公共源极线。