公开(公告)号：US08368136B2

公开(公告)日：2013-02-05

申请号：US12256132

申请日：2008-10-22

申请人： Harry Chuang ,  Tzung-Chi Lee ,  Kong-Beng Thei ,  Sheng-Chen Chung ,  Mong-Song Liang

发明人： Harry Chuang ,  Tzung-Chi Lee ,  Kong-Beng Thei ,  Sheng-Chen Chung ,  Mong-Song Liang

IPC分类号： H01L27/04

CPC分类号： H01L27/0629 ,  H01L27/11 ,  H01L29/94

摘要： A semiconductor device is provided which includes a semiconductor substrate having a first region and a second region, transistors having metal gates formed in the first region, and at least one capacitor formed in the second region. The capacitor includes a top electrode having at least one stopping structure formed in the top electrode, the at least one stopping structure being of a different material from the top electrode, a bottom electrode, and a dielectric layer interposed between the top electrode and the bottom electrode.

摘要翻译： 提供一种半导体器件，其包括具有第一区域和第二区域的半导体衬底，在第一区域中形成有金属栅极的晶体管，以及形成在第二区域中的至少一个电容器。 所述电容器包括顶电极，所述顶电极具有形成在所述顶电极中的至少一个止动结构，所述至少一个止动结构与所述顶电极，底电极和介于所述顶电极和所述底电极之间的电介质层具有不同的材料 电极。

公开(公告)号：US20120286368A1

公开(公告)日：2012-11-15

申请号：US13558109

申请日：2012-07-25

申请人： Harry Chuang ,  Kong-Beng Thei ,  Jen-Bin Hsu ,  Chung Long Cheng ,  Mong Song Liang

发明人： Harry Chuang ,  Kong-Beng Thei ,  Jen-Bin Hsu ,  Chung Long Cheng ,  Mong Song Liang

IPC分类号： H01L27/088

CPC分类号： H01L27/0207 ,  H01L27/11 ,  H01L27/1104

摘要： A semiconductor structure includes an array of unit metal-oxide-semiconductor (MOS) devices arranged in a plurality of rows and a plurality of columns is provided. Each of the unit MOS devices includes an active region laid out in a row direction and a gate electrode laid out in a column direction. The semiconductor structure further includes a first unit MOS device in the array and a second unit MOS device in the array, wherein active regions of the first and the second unit MOS devices have different conductivity types.

摘要翻译： 半导体结构包括以多行排列的单位金属氧化物半导体（MOS）器件的阵列，并且提供多个列。 每个单位MOS器件包括布置在行方向上的有源区和沿列方向布置的栅电极。 半导体结构还包括阵列中的第一单元MOS器件和阵列中的第二单元MOS器件，其中第一和第二单位MOS器件的有源区具有不同的导电类型。

公开(公告)号：US20100117190A1

公开(公告)日：2010-05-13

申请号：US12270717

申请日：2008-11-13

申请人： Harry CHUANG ,  Kong-Beng Thei ,  Sheng-Chen Chung ,  Mong-Song Liang

发明人： Harry CHUANG ,  Kong-Beng Thei ,  Sheng-Chen Chung ,  Mong-Song Liang

IPC分类号： H01L21/768 ,  H01L23/525

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A fuse structure for an IC device and methods of fabricating the structure are provided. The fuse structure comprises a metal-containing conductive strip formed over a portion of a semiconductor substrate. A dielectric layer is formed over the semiconductor substrate, covering the conductive strip. A first interconnect and a second interconnect are formed in vias extending through the dielectric layer, each physically and electrically connecting to a part of the conductive layer. First and second wiring structures are formed over the dielectric layer in electrical contact with the first and second interconnects respectively. The contact area between one of the interconnects and the strip is chosen so that electromigration will occur when a pre-selected current is applied to the fuse structure.

摘要翻译： 提供了一种用于IC器件的熔丝结构及其制造方法。 熔丝结构包括在半导体衬底的一部分上形成的含金属的导电条。 在半导体衬底上形成介电层，覆盖导电带。 第一互连和第二互连形成在延伸穿过介电层的通孔中，每个物理和电连接到导电层的一部分。 第一和第二布线结构形成在电介质层上，分别与第一和第二互连电接触。 选择互连和条之一之间的接触面积，使得当将预选电流施加到熔丝结构时，将发生电迁移。

公开(公告)号：US20100013029A1

公开(公告)日：2010-01-21

申请号：US12176133

申请日：2008-07-18

申请人： Harry Chuang ,  Hung-Chih Tsai ,  Keh-Chiang Ku ,  Kong-Beng Thei ,  Mong Song Liang

发明人： Harry Chuang ,  Hung-Chih Tsai ,  Keh-Chiang Ku ,  Kong-Beng Thei ,  Mong Song Liang

IPC分类号： H01L29/78 ,  H01L21/44

CPC分类号： H01L29/4983 ,  H01L21/28518 ,  H01L21/28525 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

摘要： A device and a method for forming a metal silicide is presented. A device, which includes a gate region, a source region, and a drain region, is formed on a substrate. A metal is disposed on the substrate, followed by a first anneal, forming a metal silicide on at least one of the gate region, the source region, and the drain region. The unreacted metal is removed from the substrate. The metal silicide is implanted with atoms. The implant is followed by a super anneal of the substrate.

摘要翻译： 提出了一种用于形成金属硅化物的器件和方法。 在基板上形成包括栅极区域，源极区域和漏极区域的器件。 在基板上设置金属，接着进行第一退火，在栅极区域，源极区域和漏极区域中的至少一个上形成金属硅化物。 将未反应的金属从基材上除去。 金属硅化物被注入原子。 植入物之后是衬底的超退火。

公开(公告)号：US20090236633A1

公开(公告)日：2009-09-24

申请号：US12052389

申请日：2008-03-20

申请人： Harry Chuang ,  Hung-Chih Tsai ,  Kong-Beng Thei ,  Mong-Song Liang

发明人： Harry Chuang ,  Hung-Chih Tsai ,  Kong-Beng Thei ,  Mong-Song Liang

IPC分类号： H01L27/092

CPC分类号： H01L21/8238 ,  H01L21/823864 ,  H01L27/11 ,  H01L27/1104

摘要： A novel SRAM memory cell structure and method of making the same are provided. The SRAM memory cell structure comprises strained PMOS transistors formed in a semiconductor substrate. The PMOS transistors comprise epitaxial grown source/drain regions that result in significant PMOS transistor drive current increase. An insulation layer is formed atop an STI that is used to electrically isolate adjacent PMOS transistors. The insulation layer is substantially elevated from the semiconductor substrate surface. The elevated insulation layer facilitates the formation of desirable thick epitaxial source/drain regions, and prevents the bridging between adjacent epitaxial layers due to the epitaxial layer lateral extension during the process of growing epitaxial sour/drain regions. The processing steps of forming the elevated insulation layer are compatible with a conventional CMOS process flow.

摘要翻译： 提供了一种新颖的SRAM存储单元结构及其制造方法。 SRAM存储单元结构包括形成在半导体衬底中的应变PMOS晶体管。 PMOS晶体管包括导致显着的PMOS晶体管驱动电流增加的外延生长的源极/漏极区域。 绝缘层形成在用于电隔离相邻PMOS晶体管的STI之上。 绝缘层基本上从半导体衬底表面升高。 升高的绝缘层有助于形成期望的厚的外延源/漏极区，并且由于在生长外延酸/漏区域的过程中由于外延层侧向延伸而防止相邻外延层之间的桥接。 形成升高的绝缘层的处理步骤与传统的CMOS工艺流程兼容。

公开(公告)号：US20080169484A1

公开(公告)日：2008-07-17

申请号：US11849798

申请日：2007-09-04

申请人： Harry Chuang ,  Kong-Beng Thei ,  Wen-Huei Guo ,  Mong Song Liang

发明人： Harry Chuang ,  Kong-Beng Thei ,  Wen-Huei Guo ,  Mong Song Liang

IPC分类号： H01L27/092 ,  H01L29/778

CPC分类号： H01L21/823807 ,  H01L29/7843

摘要： A strain-induced layer is formed atop a MOS device in order to increase carrier mobility in the channel region. The dimension of the strain-induced layer in preferred embodiments may lead to an optimized drive current increase and improved drive current uniformity in an NMOS and PMOS device. An advantage of the preferred embodiments is that improved device performance is obtained without adding complex processing steps. A further advantage of the preferred embodiments is that the added processing steps can be readily integrated into a known CMOS process flow. Moreover, the creation of the photo masks defining the tensile and compressive strain-induced layers does not require extra design work on an existed design database.

摘要翻译： 应变感应层形成在MOS器件的顶部，以增加沟道区中的载流子迁移率。 在优选实施例中，应变诱导层的尺寸可导致优化的驱动电流增加和改进的NMOS和PMOS器件中的驱动电流均匀性。 优选实施例的优点是在不添加复杂的处理步骤的情况下获得改进的设备性能。 优选实施例的另一个优点是附加的处理步骤可以容易地集成到已知的CMOS工艺流程中。 此外，创建定义拉伸和压缩应变诱导层的光罩不需要对现有设计数据库进行额外的设计工作。

公开(公告)号：US20080076215A1

公开(公告)日：2008-03-27

申请号：US11527616

申请日：2006-09-27

申请人： Harry Chuang ,  Kong-Beng Thei ,  Chung-Long Cheng ,  Sheng-Chen Chung ,  Wen-Huei Guo ,  Jung-Hui Kao ,  Ryan Chia-Jen Chen ,  Mong-Song Liang

发明人： Harry Chuang ,  Kong-Beng Thei ,  Chung-Long Cheng ,  Sheng-Chen Chung ,  Wen-Huei Guo ,  Jung-Hui Kao ,  Ryan Chia-Jen Chen ,  Mong-Song Liang

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/7843

摘要： A method of manufacturing a semiconductor device is disclosed. The method provides a semiconductor substrate with at least a PMOS device and at least an NMOS device thereon. A first insulating layer is formed overlying the NMOS and PMOS devices. A second insulating layer is formed overlying the first insulating layer. The second insulating layer overlying the PMOS device is thinned to leave portion of the second insulating layer. A first thermal treatment is performed on the NMOS and PMOS devices. The second insulating layer overlying the NMOS device and the remaining portion of the second insulating layer overlying the PMOS device are removed and the first insulating layer overlying the NMOS and PMOS devices is thinned to leave a remaining portion thereof.

摘要翻译： 公开了制造半导体器件的方法。 该方法提供具有至少PMOS器件和至少NMOS器件的半导体衬底。 在NMOS和PMOS器件上形成第一绝缘层。 在第一绝缘层上形成第二绝缘层。 覆盖PMOS器件的第二绝缘层变薄以留下第二绝缘层的部分。 在NMOS和PMOS器件上进行第一次热处理。 去除覆盖NMOS器件的第二绝缘层和覆盖PMOS器件的第二绝缘层的剩余部分，并且覆盖NMOS和PMOS器件的第一绝缘层变薄以留下其余部分。

公开(公告)号：US20110059601A1

公开(公告)日：2011-03-10

申请号：US12944221

申请日：2010-11-11

申请人： Chiung-Han Yeh ,  Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang

发明人： Chiung-Han Yeh ,  Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang

IPC分类号： H01L21/768 ,  H01L21/8234

CPC分类号： H01L21/823842 ,  H01L21/28088 ,  H01L29/517 ,  H01L29/66545

摘要： A method of fabricating a semiconductor device includes forming a first trench and a second trench on a semiconductor substrate and forming a first metal layer in the first and second trenches. The first metal layer is then removed, at least partially, from within the first trench but not the second trench. A second metal layer and a third metal layer are formed in the first and second trenches. A thermal process is used to reflow the second metal layer and the third metal layer

摘要翻译： 制造半导体器件的方法包括在半导体衬底上形成第一沟槽和第二沟槽，并在第一和第二沟槽中形成第一金属层。 然后至少部分地从第一沟槽内除去第一金属层而不是第二沟槽。 在第一和第二沟槽中形成第二金属层和第三金属层。 使用热处理来回流第二金属层和第三金属层

公开(公告)号：US20100068877A1

公开(公告)日：2010-03-18

申请号：US12488960

申请日：2009-06-22

申请人： Chiung-Han Yeh ,  Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang

发明人： Chiung-Han Yeh ,  Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang

IPC分类号： H01L21/28

CPC分类号： H01L21/823842 ,  H01L21/28088 ,  H01L29/517 ,  H01L29/66545

摘要： The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming first and second transistors in the substrate, the first transistor having a first gate structure that includes a first dummy gate, the second transistor having a second gate structure that includes a second dummy gate, removing the first and second dummy gates thereby forming a first trench and a second trench, respectively, forming a first metal layer to partially fill in the first and second trenches, removing the first metal layer within the first trench, forming a second metal layer to partially fill in the first and second trenches, forming a third metal layer to partially fill in the first and second trenches, reflowing the second metal layer and the third metal layer, and forming a fourth metal layer to fill in the remainder of the first and second trenches.

摘要翻译： 本公开提供一种制造半导体器件的方法，该半导体器件包括提供半导体衬底，在衬底中形成第一和第二晶体管，第一晶体管具有包括第一虚拟栅极的第一栅极结构，第二晶体管具有第二栅极结构 包括第二伪栅极，去除第一和第二伪栅极，从而分别形成第一沟槽和第二沟槽，形成第一金属层以部分地填充在第一和第二沟槽中，去除第一沟槽内的第一金属层 形成第二金属层以部分地填充在第一和第二沟槽中，形成第三金属层以部分地填充在第一和第二沟槽中，回流第二金属层和第三金属层，以及形成第四金属层以填充 在第一和第二个沟槽的剩余部分。

公开(公告)号：US08461629B2

公开(公告)日：2013-06-11

申请号：US13178755

申请日：2011-07-08

申请人： Chung Long Cheng ,  Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang ,  Mong-Song Liang

发明人： Chung Long Cheng ,  Sheng-Chen Chung ,  Kong-Beng Thei ,  Harry Chuang ,  Mong-Song Liang

IPC分类号： H01L29/66

CPC分类号： H01L29/66477 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823462 ,  H01L27/0629 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/7848

摘要： A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an isolation structure. An I/O device is formed over the I/O well and has a silicon dioxide or a low-k gate dielectric. A resistor may be formed on an isolation structure adjacent to the core well. A core-well device such as a transistor is formed over the core well, and has a high-k gate dielectric. In some embodiments, a p-type I/O well and an n-type I/O well are created. In a preferred embodiment, the I/O device or devices are formed prior to forming the core device and protected with a sacrificial layer until the core device is fabricated.

摘要翻译： 具有具有高k栅极电介质的核心器件和具有二氧化硅或其它非高k栅极电介质的I / O器件的半导体器件及其制造方法。 核心阱和I / O阱在半导体衬底中产生并被隔离结构隔开。 I / O器件形成在I / O阱上，并具有二氧化硅或低k栅极电介质。 可以在与芯井相邻的隔离结构上形成电阻器。 在核心阱上形成诸如晶体管的核心阱器件，并且具有高k栅极电介质。 在一些实施例中，产生p型I / O阱和n型I / O阱。 在优选实施例中，在形成核心器件之前形成I / O器件或器件，并用牺牲层进行保护，直到制造核心器件。