公开(公告)号：US20080016306A1

公开(公告)日：2008-01-17

申请号：US11567844

申请日：2006-12-07

申请人： Byung-Jun Min ,  Kang-Woon Lee ,  Han-Joo Lee ,  Byung-Gil Jeon

发明人： Byung-Jun Min ,  Kang-Woon Lee ,  Han-Joo Lee ,  Byung-Gil Jeon

IPC分类号： G06F12/14 ,  G06F12/00

CPC分类号： G06F12/0638

摘要： A semiconductor memory having two different memory areas in one chip includes a memory cell array including a first variable memory area controlled to be accessible in at least first and second operation modes, and a second variable memory area controlled to be inaccessible in owe of the first and second operation modes; and a memory control unit for storing area information discriminating between the first memory area and the second memory area and generating memory control signals for controlling access to the first memory area and the second memory area. One memory can be substituted for a memory combination including ROMs and RAMs in one chip.

摘要翻译： 在一个芯片中具有两个不同存储区域的半导体存储器包括存储单元阵列，该存储单元阵列包括被控制为在至少第一和第二操作模式中可访问的第一可变存储区，以及被控制为不可访问的第一可变存储区， 和第二操作模式; 以及存储器控制单元，用于存储识别第一存储区域和第二存储区域之间的区域信息，并产生用于控制对第一存储区域和第二存储区域的访问的存储器控​​制信号。 一个存储器可以替代包括一个芯片中的ROM和RAM的存储器组合。

公开(公告)号：US07085158B2

公开(公告)日：2006-08-01

申请号：US10787369

申请日：2004-02-26

申请人： Byung-Gil Jeon ,  Byung-Jun Min

发明人： Byung-Gil Jeon ,  Byung-Jun Min

IPC分类号： G11C11/34 ,  G11C17/00

CPC分类号： G11C7/20 ,  G11C16/20

摘要： A nonvolatile semiconductor memory device is provided, comprising a nonvolatile memory cell array which has a one-time programming region accessed in response to a first decoding signal and a normal region accessed in response to a second decoding signal. The device performs a read operation and a write operation. The device further comprises (a) a data write circuit writing data in the nonvolatile memory cell array in response to a write enable signal during the write operation; (b) a data read circuit reading data output from the nonvolatile memory cell array in response to a sense amplifier enable signal during the read operation; and (c) a control means activating the sense amplifier enable signal when the first decoding signal is generated and comparing data output from the data read circuit to generate the write enable signal during the write operation.

摘要翻译： 提供了一种非易失性半导体存储器件，其包括非易失性存储单元阵列，其具有响应于第一解码信号和响应于第二解码信号访问的正常区域而被访问的一次编程区域。 设备执行读操作和写操作。 该装置还包括（a）在写入操作期间响应于写使能信号在非易失性存储单元阵列中写入数据的数据写入电路; （b）数据读取电路，在读取操作期间响应于读出放大器使能信号读取从非易失性存储单元阵列输出的数据; 和（c）在产生第一解码信号时激活读出放大器使能信号的控制装置，并且比较在写入操作期间从数据读取电路输出的数据以产生写使能信号。

公开(公告)号：US07075812B2

公开(公告)日：2006-07-11

申请号：US11053649

申请日：2005-02-08

申请人： Byung-Jun Min ,  Byung-Gil Jeon

发明人： Byung-Jun Min ,  Byung-Gil Jeon

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： There are provided a ferroelectric RAM (Random Access Memory) device and a control method thereof. In the device, a data input buffer circuit senses a transition of input data and generates a data transition detection signal. Further, a plate pulse generator generates a single pulse to store first logic data among applied data at an enable section of a plate line, and to store second logic data opposite to the first logic data at a disable section of the plate line, where the single pulse enables the plate line connected to a memory cell in response to the data transition detection signal and then disables it after lapse of a given time. Thus, a stabilized write operation can be provided and a control of the ferroelectric RAM device can be simplified.

摘要翻译： 提供了一种铁电RAM（Random Access Memory：随机存取存储器）装置及其控制方法。 在该装置中，数据输入缓冲器电路检测输入数据的转变并产生数据转换检测信号。 此外，平板脉冲发生器产生单个脉冲，以在板线的使能部分处应用数据之间存储第一逻辑数据，并且在板线的禁用部分处存储与第一逻辑数据相反的第二逻辑数据，其中 单脉冲使得能够响应于数据转换检测信号而连接到存储单元的板线，然后在经过给定时间之后禁用它。 因此，可以提供稳定的写入操作，并且可以简化铁电RAM器件的控制。

公开(公告)号：US20060126372A1

公开(公告)日：2006-06-15

申请号：US11301920

申请日：2005-12-13

申请人： Kang-Woon Lee ,  Byung-Jun Min ,  Han-Joo Lee ,  Byung-Gil Jeon

发明人： Kang-Woon Lee ,  Byung-Jun Min ,  Han-Joo Lee ,  Byung-Gil Jeon

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： A drive circuit of a FRAM (Ferroelectric Random Access Memory) includes an address buffer circuit that buffers an applied external address signal and generates an internal address signal, and detects a transition of the internal address signal and generates address transition detection signals for respective internal address signals. The FRAM includes a composite pulse signal generating circuit which limits a subsequent generation of a composite pulse signal for a delay interval provided after a generation of a previous composite pulse signal, in generating the second composite pulse signal obtained by totaling the respective address transition detection signals. The FRAM includes an internal chip enable buffer circuit which generates an internal chip enable signal to generate an internal control signal, in response to the composite pulse signal.

摘要翻译： FRAM（铁电随机存取存储器）的驱动电路包括缓存施加的外部地址信号并产生内部地址信号的地址缓冲器电路，并检测内部地址信号的转换，并产生各自内部地址的地址转换检测信号 信号。 FRAM包括复合脉冲信号发生电路，其在生成先前的复合脉冲信号之后，在产生通过对各个地址转换检测信号进行合并而获得的第二复合脉冲信号的同时限制复合脉冲信号的后续生成， 。 FRAM包括内部芯片使能缓冲电路，其响应于复合脉冲信号而产生内部芯片使能信号以产生内部控制信号。

公开(公告)号：US20060092725A1

公开(公告)日：2006-05-04

申请号：US11238198

申请日：2005-09-29

申请人： Byung-Jun Min ,  Kang-Woon Lee ,  Han-Joo Lee ,  Byung-Gil Jeon

发明人： Byung-Jun Min ,  Kang-Woon Lee ,  Han-Joo Lee ,  Byung-Gil Jeon

IPC分类号： G11C29/00

CPC分类号： G11C29/789 ,  G11C29/787

摘要： A redundancy circuit and repair method for a semiconductor memory device. The redundancy circuit comprises an address buffer for outputting a first internal address and a second internal address (used only during redundancy programming to carry failed memory addresses) based on an external address; and address storage and comparison units, each one of the address storage and comparison units being selected for programming using the second internal address. The address storage and comparison units comprise ferroelectric storage cells that store the address of a defective (failed) main memory cell and outputs a redundancy decoder enable signal in response to a first internal address matching the stored (second internal) address. Accordingly, the redundancy circuit with ferroelectric storage cells and a repair method allows the performance of a second repair when a defective cell is detected after a first repair or after a packaging process.

摘要翻译： 一种用于半导体存储器件的冗余电路和修复方法。 冗余电路包括用于基于外部地址输出第一内部地址和第二内部地址（仅在冗余编程中使用以携带失败的存储器地址）的地址缓冲器; 以及地址存储和比较单元，使用第二内部地址选择每个地址存储和比较单元进行编程。 地址存储和比较单元包括存储故障（故障）主存储单元的地址的铁电存储单元，并且响应于与存储的（第二内部）地址匹配的第一内部地址而输出冗余解码器使能信号。 因此，具有铁电存储单元的冗余电路和修复方法允许在第一修复或包装处理之后检测到缺陷单元时执行第二次修复。

公开(公告)号：US20060077740A1

公开(公告)日：2006-04-13

申请号：US11212311

申请日：2005-08-26

申请人： Kang-Woon Lee ,  Byung Min ,  Han-Joo Lee ,  Byung-Gil Jeon

发明人： Kang-Woon Lee ,  Byung Min ,  Han-Joo Lee ,  Byung-Gil Jeon

IPC分类号： G11C7/02

CPC分类号： G11C11/22 ,  G11C7/06 ,  G11C7/14 ,  G11C2207/2227

摘要： A reference voltage supply apparatus and a driving method thereof in a ferroelectric memory device provide a reference voltage stabilized against the imprint effect thus maintaining reading reliability of the device. In the reference voltage supply apparatus (e.g., using a non-switching capacitance of a ferroelectric capacitor), a reference cell is constructed of a ferroelectric capacitor and an access switch, and provides a reference voltage to read data from a memory cell. In an active mode, the reference cell stores data of a first logic state (e.g., corresponding to the non-switching capacitance of the ferroelectric capacitor), in the reference cell, and then supplies, as a reference voltage, the voltage corresponding to the data of the first logic state to a bit line; and in a stand-by mode, a reference voltage controller stores (writes) data of a second logic state (opposite to the first logic state), into the reference cell.

公开(公告)号：US20050174831A1

公开(公告)日：2005-08-11

申请号：US11053649

申请日：2005-02-08

申请人： Byung-Jun Min ,  Byung-Gil Jeon

发明人： Byung-Jun Min ,  Byung-Gil Jeon

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： There are provided a ferroelectric RAM (Random Access Memory) device and a control method thereof. In the device, a data input buffer circuit senses a transition of input data and generates a data transition detection signal. Further, a plate pulse generator generates a single pulse to store first logic data among applied data at an enable section of a plate line, and to store second logic data opposite to the first logic data at a disable section of the plate line, where the single pulse enables the plate line connected to a memory cell in response to the data transition detection signal and then disables it after lapse of a given time. Thus, a stabilized write operation can be provided and a control of the ferroelectric RAM device can be simplified.

摘要翻译： 提供了一种铁电RAM（Random Access Memory：随机存取存储器）装置及其控制方法。 在该装置中，数据输入缓冲器电路检测输入数据的转变并产生数据转换检测信号。 此外，平板脉冲发生器产生单个脉冲，以在板线的使能部分处应用数据之间存储第一逻辑数据，并且在板线的禁用部分处存储与第一逻辑数据相反的第二逻辑数据，其中 单脉冲使得能够响应于数据转换检测信号而连接到存储单元的板线，然后在经过给定时间之后禁用它。 因此，可以提供稳定的写入操作，并且可以简化铁电RAM器件的控制。

公开(公告)号：US20050135143A1

公开(公告)日：2005-06-23

申请号：US11015428

申请日：2004-12-16

申请人： Byung-Gil Jeon

发明人： Byung-Gil Jeon

IPC分类号： H01L27/105 ,  G11C11/22

CPC分类号： G11C11/22

摘要： A ferroelectric RAM (Random Access Memory) device includes at least one memory cell constructed of one access transistor operating by a word line enable signal, and one ferroelectric capacitor connected between a bit line and the access transistor. The device has a cell array structure based on a repeated array of the memory cells. The device also includes a word line driver suitable for a high integration and reducing power consumption. The driving method in the ferroelectric RAM device generates a word line enable signal having a level of power source voltage, to read and write data. The method has advantages of being suitable for a high integration, enhancing an operating speed and reducing power consumption and providing stabilized read and write operations.

摘要翻译： 铁电RAM（随机存取存储器）装置包括至少一个由字线使能信号操作的存取晶体管构成的存储单元和连接在位线与存取晶体管之间的一个铁电电容器。 该器件具有基于存储器单元的重复阵列的单元阵列结构。 该装置还包括适用于高集成度和降低功耗的字线驱动器。 铁电RAM器件中的驱动方法产生具有电源电压电平的字线使能信号，以读取和写入数据。 该方法具有适用于高集成度，提高操作速度和降低功耗以及提供稳定的读写操作的优点。

公开(公告)号：US06504749B2

公开(公告)日：2003-01-07

申请号：US10005445

申请日：2001-12-03

申请人： Byung-Gil Jeon

发明人： Byung-Gil Jeon

IPC分类号： G11C1122

CPC分类号： G11C11/22

摘要： A ferroelectric memory device comprises a plurality of parallel word lines extending along a first direction, a plurality of parallel bit lines extending along a second direction transverse to the first direction, and a plurality of parallel plate lines extending along the first direction. A plurality of memory cells is arranged in rows and columns along the respective first and second directions, each of the memory cells including a transistor coupled to one of the word lines and to one of the bit lines and a ferroelectric capacitor connected to the transistor and to one of the plate lines such cells in respective rows are connected to respective word lines and that the ferroelectric capacitors of first and second subsets of a row of memory cells are connected to respective first and second plate lines.

公开(公告)号：US09903901B2

公开(公告)日：2018-02-27

申请号：US14681137

申请日：2015-04-08

申请人： Byung-Gil Jeon ,  Doo-Gon Kim

发明人： Byung-Gil Jeon ,  Doo-Gon Kim

IPC分类号： G01R31/02 ,  G11C29/02 ,  G11C29/50 ,  G11C11/16 ,  G11C13/00

CPC分类号： G01R31/025 ,  G11C11/1673 ,  G11C13/00 ,  G11C29/023 ,  G11C29/025 ,  G11C29/026 ,  G11C29/50008 ,  G11C2029/5006

摘要： A leakage current detection device includes a test detection circuit, a reference detection circuit, a comparator, and a latch circuit. The test detection circuit is coupled between a test node and a test line, provides a voltage to the test node to charge the test line, floats the test node and the test line, and decreases a voltage of the test node based on leakage current of the test line. The reference detection circuit is coupled between a reference node and a reference line, provides the voltage to the reference node to charge the reference line, floats the reference node and the reference line, and decreases a voltage of the reference node based on self-discharge of the reference line. The comparator outputs a comparison signal by comparing voltages of the test node and the reference node. The latch circuit latches the comparison signal to output a test result signal.