公开(公告)号：US20090052224A1

公开(公告)日：2009-02-26

申请号：US12228590

申请日：2008-08-14

申请人： Byung-Jun Min ,  Kang-Woon Lee ,  Han-Joo Lee ,  Byung-Gil Jeon

发明人： Byung-Jun Min ,  Kang-Woon Lee ,  Han-Joo Lee ,  Byung-Gil Jeon

IPC分类号： G11C11/22 ,  G11C7/00 ,  G11C7/06

CPC分类号： G11C7/1018 ,  G11C7/08 ,  G11C11/22

摘要： In a ferroelectric random access memory device that can allow a stable burst read operation and a method of driving a ferroelectric random access memory device thereof, the ferroelectric random access memory device comprises first and second memory cell sections, each comprising a plurality of ferroelectric memory cells, and a read circuit that sequentially performs a burst read operation on the first and second memory cell sections such that a read operation of the first memory cell section partially overlaps a read operation of the second memory cell section. When a chip is disabled during the read operation of the first memory cell section, the read circuit writes back data in the second memory cell section in response to the extent to which the read operation of the second memory cell section has been performed.

摘要翻译： 在能够进行稳定的脉冲串读取操作的铁电随机存取存储器件和驱动其铁电随机存取存储器件的方法中，铁电随机存取存储器件包括第一和第二存储单元部分，每个存储单元包括多个铁电存储单元 以及读取电路，其顺序地对第一和第二存储单元部分执行突发读取操作，使得第一存储单元部分的读取操作部分地与第二存储器单元部分的读取操作重叠。 当在第一存储器单元部分的读取操作期间芯片被禁止时，读取电路响应于执行第二存储器单元部分的读取操作的程度将数据写回第二存储器单元部分。

公开(公告)号：US07336549B2

公开(公告)日：2008-02-26

申请号：US11238198

申请日：2005-09-29

申请人： Byung-Jun Min ,  Kang-Woon Lee ,  Han-Joo Lee ,  Byung-Gil Jeon

发明人： Byung-Jun Min ,  Kang-Woon Lee ,  Han-Joo Lee ,  Byung-Gil Jeon

IPC分类号： G11C7/00

CPC分类号： G11C29/789 ,  G11C29/787

摘要： A redundancy circuit and repair method for a semiconductor memory device. The redundancy circuit comprises an address buffer for outputting a first internal address and a second internal address (used only during redundancy programming to carry failed memory addresses) based on an external address; and address storage and comparison units, each one of the address storage and comparison units being selected for programming using the second internal address. The address storage and comparison units comprise ferroelectric storage cells that store the address of a defective (failed) main memory cell and outputs a redundancy decoder enable signal in response to a first internal address matching the stored (second internal) address. Accordingly, the redundancy circuit with ferroelectric storage cells and a repair method allows the performance of a second repair when a defective cell is detected after a first repair or after a packaging process.

摘要翻译： 一种用于半导体存储器件的冗余电路和修复方法。 冗余电路包括用于基于外部地址输出第一内部地址和第二内部地址（仅在冗余编程中使用以携带失败的存储器地址）的地址缓冲器; 以及地址存储和比较单元，使用第二内部地址选择每个地址存储和比较单元进行编程。 地址存储和比较单元包括存储故障（故障）主存储单元的地址的铁电存储单元，并且响应于与存储的（第二内部）地址匹配的第一内部地址而输出冗余解码器使能信号。 因此，具有铁电存储单元的冗余电路和修复方法允许在第一修复或包装处理之后检测到缺陷单元时执行第二次修复。

公开(公告)号：US20050174830A1

公开(公告)日：2005-08-11

申请号：US11038304

申请日：2005-01-19

申请人： Kang-Woon Lee ,  Byung-Jun Min ,  Byung-Gil Jeon

发明人： Kang-Woon Lee ,  Byung-Jun Min ,  Byung-Gil Jeon

IPC分类号： G11C5/14 ,  G11C11/22

CPC分类号： G11C11/22 ,  G11C5/147

摘要： A reference voltage generating apparatus and a driving method therefor are provided. The method of driving the reference voltage generating apparatus for supplying a reference voltage to read data from a ferroelectric memory cell including a ferroelectric capacitor and an access transistor comprises: re-storing, in a reference cell, data equal to data stored in the reference cell, in response to a first control signal, and generating a reference voltage, in the re-stored reference cell, in response to a second control signal, to compare the reference voltage with a voltage corresponding to data stored in the ferroelectric memory cell and to read the data stored in the ferroelectric memory cell. The reference cell includes a ferroelectric capacitor and an access transistor.

摘要翻译： 提供了一种参考电压产生装置及其驱动方法。 驱动用于提供参考电压以从包括铁电电容器和存取晶体管的铁电存储器单元读取数据的参考电压产生装置的方法包括：在参考单元中重新存储与存储在参考单元中的数据相同的数据 响应于第一控制信号，并且在重新存储的参考单元中产生参考电压，响应于第二控制信号，将参考电压与对应于存储在铁电存储单元中的数据的电压进行比较，以及 读取存储在铁电存储单元中的数据。 参考单元包括铁电电容器和存取晶体管。

公开(公告)号：US20050013162A1

公开(公告)日：2005-01-20

申请号：US10787369

申请日：2004-02-26

申请人： Byung-Gil Jeon ,  Byung-Jun Min

发明人： Byung-Gil Jeon ,  Byung-Jun Min

IPC分类号： G11C16/00 ,  G11C7/20 ,  G11C16/20 ,  G11C16/04

CPC分类号： G11C7/20 ,  G11C16/20

摘要： A nonvolatile semiconductor memory device is provided, comprising a nonvolatile memory cell array which has a one-time programming region accessed in response to a first decoding signal and a normal region accessed in response to a second decoding signal. The device performs a read operation and a write operation. The device further comprises (a) a data write circuit writing data in the nonvolatile memory cell array in response to a write enable signal during the write operation; (b) a data read circuit reading data output from the nonvolatile memory cell array in response to a sense amplifier enable signal during the read operation; and (c) a control means activating the sense amplifier enable signal when the first decoding signal is generated and comparing data output from the data read circuit to generate the write enable signal during the write operation.

摘要翻译： 提供了一种非易失性半导体存储器件，其包括非易失性存储单元阵列，其具有响应于第一解码信号和响应于第二解码信号访问的正常区域而被访问的一次编程区域。 设备执行读操作和写操作。 该装置还包括（a）在写入操作期间响应于写使能信号在非易失性存储单元阵列中写入数据的数据写入电路; （b）数据读取电路，在读取操作期间响应于读出放大器使能信号读取从非易失性存储单元阵列输出的数据; 和（c）在产生第一解码信号时激活读出放大器使能信号的控制装置，并且比较在写入操作期间从数据读取电路输出的数据以产生写使能信号。

公开(公告)号：US07345945B2

公开(公告)日：2008-03-18

申请号：US11232170

申请日：2005-09-21

申请人： Byung-Gil Jeon ,  Byung-Jun Min ,  Kang-Woon Lee ,  Han-Joo Lee

发明人： Byung-Gil Jeon ,  Byung-Jun Min ,  Kang-Woon Lee ,  Han-Joo Lee

IPC分类号： G11C8/00

CPC分类号： G11C8/08 ,  G11C8/14

摘要： A semiconductor memory device having a word line driver circuit configured in stages. A plurality of sub word line driver circuits are connected, in parallel, to each main word line, and provide a sub word line enable signal to a selected sub word line in response to a main word line enable signal provided through a main word line. A plurality of (local) word line driver circuits are connected in parallel, to each sub word line and provide a local word line enable signal to a selected local word line in response to the (main/sub) word line enable signal so as to operate a plurality of memory cells connected to the selected local word line. The transistor count and layout area of a semiconductor memory device decreases and a reduced chip area can be achieved.

摘要翻译： 具有分级配置的字线驱动电路的半导体存储装置。 多个子字线驱动器电路并联连接到每个主字线，并且响应于通过主字线提供的主字线使能信号，向所选择的子字线提供子字线使能信号。 多个（本地）字线驱动电路并联连接到每个子字线，并响应于（主/副）字线使能信号而向所选择的本地字线提供本地字线使能信号，以便 操作连接到所选择的本地字线的多个存储器单元。 半导体存储器件的晶体管数量和布局面积减小，芯片面积减小。

公开(公告)号：US20070035983A1

公开(公告)日：2007-02-15

申请号：US11484280

申请日：2006-07-11

申请人： Kang-Woon Lee ,  Byung-Jun Min ,  Han-Joo Lee ,  Byung-Gil Jeon

发明人： Kang-Woon Lee ,  Byung-Jun Min ,  Han-Joo Lee ,  Byung-Gil Jeon

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： A FeRAM device and a writing section control method therefor, in which the device includes a memory cell constructed of one access transistor and one ferroelectric capacitor; and a writing control circuit for controlling a first writing section to write data of a first logic state in the memory cell and a second writing section to write data of a second logic state different from the first logic state, in response to an external clock signal. Thus a stabilized write operation can be performed and a reliability of data stored in the memory cell can be tested.

摘要翻译： 一种FeRAM器件及其写入部分控制方法，其中该器件包括由一个存取晶体管和一个铁电电容器构成的存储单元; 以及写入控制电路，用于响应于外部时钟信号，控制第一写入部分将存储单元中的第一逻辑状态的数据写入第二写入部分以写入与第一逻辑状态不同的第二逻辑状态的数据 。 因此，可以执行稳定的写入操作，并且可以测试存储在存储单元中的数据的可靠性。

公开(公告)号：US07173844B2

公开(公告)日：2007-02-06

申请号：US11197033

申请日：2005-08-04

申请人： Han-Joo Lee ,  Kang-Woon Lee ,  Byung-Jun Min ,  Byung-Gil Jeon

发明人： Han-Joo Lee ,  Kang-Woon Lee ,  Byung-Jun Min ,  Byung-Gil Jeon

IPC分类号： G11C11/22

CPC分类号： G11C7/04 ,  G11C5/147 ,  G11C11/22

摘要： A reference voltage generating device that provides a constant reference voltage even with temperature change in a ferroelectric random access memory and a method for driving the same are provided. A device for generating a reference voltage in a ferroelectric random access memory including memory cells, each of which has one ferroelectric capacitor and one access transistor, includes a reference cell composed of a ferroelectric capacitor and a transistor; a reference plate line connected to one end of the ferroelectric capacitor constituting the reference cell; and a reference plate line driver circuit for adjusting a voltage level of a reference plate line enable signal depending on temperature change so that a constant reference voltage is generated.

摘要翻译： 提供了即使在铁电随机存取存储器中的温度变化也提供恒定参考电压的参考电压产生装置及其驱动方法。 一种用于在具有一个铁电电容器和一个存取晶体管的存储单元的铁电随机存取存储器中产生参考电压的装置包括由铁电电容器和晶体管构成的参考电池; 连接到构成参考电池的铁电电容器的一端的参考板线; 以及用于根据温度变化调整参考板线使能信号的电压电平的参考板线驱动电路，从而产生恒定的参考电压。

公开(公告)号：US20060028890A1

公开(公告)日：2006-02-09

申请号：US11197033

申请日：2005-08-04

申请人： Han-Joo Lee ,  Kang-Woon Lee ,  Byung-Jun Min ,  Byung-Gil Jeon

发明人： Han-Joo Lee ,  Kang-Woon Lee ,  Byung-Jun Min ,  Byung-Gil Jeon

IPC分类号： G11C7/02 ,  G11C11/22

CPC分类号： G11C7/04 ,  G11C5/147 ,  G11C11/22

摘要： A reference voltage generating device that provides a constant reference voltage even with temperature change in a ferroelectric random access memory and a method for driving the same are provided. A device for generating a reference voltage in a ferroelectric random access memory including memory cells, each of which has one ferroelectric capacitor and one access transistor, includes a reference cell composed of a ferroelectric capacitor and a transistor; a reference plate line connected to one end of the ferroelectric capacitor constituting the reference cell; and a reference plate line driver circuit for adjusting a voltage level of a reference plate line enable signal depending on temperature change so that a constant reference voltage is generated.

摘要翻译： 提供了即使在铁电随机存取存储器中的温度变化也提供恒定参考电压的参考电压产生装置及其驱动方法。 一种用于在具有一个铁电电容器和一个存取晶体管的存储单元的铁电随机存取存储器中产生参考电压的装置包括由铁电电容器和晶体管构成的参考电池; 连接到构成参考电池的铁电电容器的一端的参考板线; 以及用于根据温度变化调整参考板线使能信号的电压电平的参考板线驱动电路，从而产生恒定的参考电压。

公开(公告)号：US08467244B2

公开(公告)日：2013-06-18

申请号：US12844621

申请日：2010-07-27

申请人： Byung-Gil Jeon ,  Kang-Woon Lee ,  Byung-Jun Min ,  Han-Joo Lee

发明人： Byung-Gil Jeon ,  Kang-Woon Lee ,  Byung-Jun Min ,  Han-Joo Lee

IPC分类号： G11C16/04

CPC分类号： G11C16/26 ,  G11C16/349

摘要： A flash memory device and a flash memory system are disclosed. The flash memory device includes a first non-volatile memory including a plurality of page data cells, storing page data, and reading and outputting the stored page data when a read command is applied from an external portion; and a second non-volatile memory including a plurality of spare data cells respectively adjacent to the plurality of page data cells, storing spare data, scanning the spare data and temporarily storing corresponding information when a file system is mounted, reading and outputting the stored spare data when the read command is applied.

摘要翻译： 公开了闪存设备和闪存系统。 闪速存储装置包括：第一非易失性存储器，包括多个页数据单元，存储页数据;以及当从外部部分施加读命令时，读出并输出存储的页数据; 以及第二非易失性存储器，其包括分别与所述多个页数据单元相邻的多个备用数据单元，存储备用数据，扫描备用数据并在安装文件系统时临时存储相应的信息，读取并输出所存储的备用 应用读命令时的数据。

公开(公告)号：US20100312954A1

公开(公告)日：2010-12-09

申请号：US12844621

申请日：2010-07-27

申请人： Byung-Gil Jeon ,  Kang-Woon Lee ,  Byung-Jun Min ,  Han-Joo Lee

发明人： Byung-Gil Jeon ,  Kang-Woon Lee ,  Byung-Jun Min ,  Han-Joo Lee

IPC分类号： G06F12/02 ,  H01L23/52 ,  G06F12/00

CPC分类号： G11C16/26 ,  G11C16/349

摘要： A flash memory device and a flash memory system are disclosed. The flash memory device includes a first non-volatile memory including a plurality of page data cells, storing page data, and reading and outputting the stored page data when a read command is applied from an external portion; and a second non-volatile memory including a plurality of spare data cells respectively adjacent to the plurality of page data cells, storing spare data, scanning the spare data and temporarily storing corresponding information when a file system is mounted, reading and outputting the stored spare data when the read command is applied.

摘要翻译： 公开了闪存设备和闪存系统。 闪速存储装置包括：第一非易失性存储器，包括多个页数据单元，存储页数据;以及当从外部部分施加读命令时，读出并输出存储的页数据; 以及第二非易失性存储器，其包括分别与所述多个页数据单元相邻的多个备用数据单元，存储备用数据，扫描备用数据并在安装文件系统时临时存储相应的信息，读取并输出所存储的备用 应用读命令时的数据。