公开(公告)号：US09426412B2

公开(公告)日：2016-08-23

申请号：US13819770

申请日：2012-05-21

申请人： Hideshi Nishida

发明人： Hideshi Nishida

IPC分类号： H04N7/01 ,  G09G5/14 ,  G09G5/393 ,  G09G5/395 ,  H04N21/431 ,  H04N5/445 ,  H04N21/426 ,  H04N21/4402 ,  G09G5/02 ,  G09G5/373 ,  G09G5/391 ,  G06T3/40

CPC分类号： H04N7/0117 ,  G06T3/4092 ,  G09G5/026 ,  G09G5/14 ,  G09G5/373 ,  G09G5/391 ,  G09G5/393 ,  G09G5/395 ,  G09G2340/0442 ,  G09G2340/10 ,  G09G2354/00 ,  H04N5/44504 ,  H04N21/42653 ,  H04N21/4314 ,  H04N21/440263

摘要： A rendering device provides improved rendering responsiveness in multi-window display for rendering scenarios in which display sizes of images vary over time, while also reducing required memory bandwidth. The device comprises: a scenario processor 101 for interpreting a rendering scenario and calculating for each frame period a scale-down ratio for each of a plurality of pictures; a plurality of decoders 107 for decoding encoded data of a plurality of videos; a plurality of first scalers for scaling-down the decoded pictures using the scale-down ratios calculated by the scenario processor 101; a memory 106 for storing the scaled-down pictures; a plurality of second scalers 113 for reading the scaled-down pictures from the memory and re-scaling the scaled-down pictures to match the scale-down ratios calculated by the scenario processor for a current frame period; and, a composing unit 115 for composing the re-scaled pictures.

摘要翻译： 渲染设备在多窗口显示中提供改进的渲染响应性，用于渲染场景，其中图像的显示尺寸随时间变化，同时还减少所需的存储器带宽。 该装置包括：场景处理器101，用于解释渲染场景，并为每个帧周期计算多个图像中的每一个的缩小比例; 多个解码器107，用于解码多个视频的编码数据; 多个第一缩放器，用于使用由所述情景处理器101计算的缩小比例来缩小所述解码图像; 用于存储缩小图像的存储器106; 多个第二定标器113，用于从存储器读取按比例缩小的图像，并重新缩放缩小图像以匹配由场景处理器为当前帧周期计算的缩小比例; 以及组合单元115，用于组合重新缩放的图片。

公开(公告)号：US08719551B2

公开(公告)日：2014-05-06

申请号：US13265172

申请日：2010-04-15

申请人： Hideshi Nishida

发明人： Hideshi Nishida

IPC分类号： G06F9/38 ,  G06F13/14

CPC分类号： G06F9/30189 ,  G06F9/3802 ,  G06F9/3851 ,  G06F9/3887 ,  G06F9/3889

摘要： The present invention provides an information processing apparatus and an integrated circuit which realize parallel execution of different processing systems, and which do not require the provision of a dedicated memory storing instructions for common processing The information processing apparatus comprises: a plurality of processor elements; an instruction memory storing a first program and a second program; and an arbiter interposed between the processor elements and the instruction memory, the arbiter receiving, from each of the processor elements, a request for an instruction, from among instructions included in the first program and the second program, and controlling access to the instruction memory by the processor elements, wherein the arbiter arbitrates requests made by the processor elements when the requests are (i) simultaneous requests for different instructions included in one of the first program and the second program or (ii) simultaneous requests for an instruction included in the first program and an instruction included in the second program, and when two or more of the processor elements simultaneously request a same instruction included in one of the first program and the second program, the arbiter, when judging that the instruction memory is available to the two or more processor elements, outputs the same instruction to the two or more processor elements.

摘要翻译： 本发明提供一种信息处理装置和集成电路，其实现不同处理系统的并行执行，并且不需要提供存储用于公共处理的指令的专用存储器。信息处理装置包括：多个处理器元件; 存储第一程序和第二程序的指令存储器; 以及插入在所述处理器元件和所述指令存储器之间的仲裁器，所述仲裁器从每个所述处理器元件从所述第一程序和所述第二程序中包括的指令中接收对指令的请求，并且控制对所述指令存储器的访问 所述处理器元件，其中所述仲裁器在所述请求是（i）对包括在所述第一程序和所述第二程序之一中的不同指令的同时请求时仲裁由所述处理器单元作出的请求，或者（ii）同时请求包括在所述第一程序和所述第二程序中的指令 第一程序和包括在第二程序中的指令，并且当两个或更多个处理器单元同时请求包括在第一程序和第二程序之一中的相同指令时，仲裁器在判断指令存储器可用于 两个或多个处理器元件向两个或多个处理器元件输出相同的指令。

公开(公告)号：US20130155185A1

公开(公告)日：2013-06-20

申请号：US13819770

申请日：2012-05-21

申请人： Hideshi Nishida

发明人： Hideshi Nishida

IPC分类号： H04N7/01

CPC分类号： H04N7/0117 ,  G06T3/4092 ,  G09G5/026 ,  G09G5/14 ,  G09G5/373 ,  G09G5/391 ,  G09G5/393 ,  G09G5/395 ,  G09G2340/0442 ,  G09G2340/10 ,  G09G2354/00 ,  H04N5/44504 ,  H04N21/42653 ,  H04N21/4314 ,  H04N21/440263

摘要： A rendering device provides improved rendering responsiveness in multi-window display for rendering scenarios in which display sizes of images vary over time, while also reducing required memory bandwidth. The device comprises: a scenario processor 101 for interpreting a rendering scenario and calculating for each frame period a scale-down ratio for each of a plurality of pictures; a plurality of decoders 107 for decoding encoded data of a plurality of videos; a plurality of first scalers for scaling-down the decoded pictures using the scale-down ratios calculated by the scenario processor 101; a memory 106 for storing the scaled-down pictures; a plurality of second scalers 113 for reading the scaled-down pictures from the memory and re-scaling the scaled-down pictures to match the scale-down ratios calculated by the scenario processor for a current frame period; and, a composing unit 115 for composing the re-scaled pictures.

摘要翻译： 渲染设备在多窗口显示中提供改进的渲染响应性，用于渲染场景，其中图像的显示尺寸随时间变化，同时还减少所需的存储器带宽。 该装置包括：场景处理器101，用于解释渲染场景，并为每个帧周期计算多个图像中的每一个的缩小比例; 多个解码器107，用于解码多个视频的编码数据; 多个第一缩放器，用于使用由所述情景处理器101计算的缩小比例来缩小所述解码图像; 用于存储缩小图像的存储器106; 多个第二定标器113，用于从存储器读取按比例缩小的图像，并重新缩放缩小图像以匹配由场景处理器为当前帧周期计算的缩小比例; 以及组合单元115，用于组合重新缩放的图片。

公开(公告)号：US08073053B2

公开(公告)日：2011-12-06

申请号：US11662783

申请日：2005-09-05

申请人： Hideshi Nishida

发明人： Hideshi Nishida

IPC分类号： H04N7/12

CPC分类号： H04N19/58 ,  H04N19/127 ,  H04N19/137 ,  H04N19/157 ,  H04N19/172 ,  H04N19/51 ,  H04N19/57 ,  H04N19/61

摘要： An image encoding device encodes moving pictures, a moving picture count acquisition unit acquires a moving picture count of encoding target moving pictures corresponding to an arbitrary number of input moving pictures, a moving picture acquisition unit acquires one or plural encoding target moving pictures, a processing method designation unit, in accordance with the acquired count, designates processing methods relating to encoding processing that affect a computation amount, and an encoding processing unit performs encoding processing with respect to the acquired one or plural moving pictures, using time division when the plural moving pictures are plural. The encoding unit performs encoding processing using the designated methods.

摘要翻译： 图像编码装置对运动图像进行编码，运动图像计数获取单元获取与任意数量的输入运动图像相对应的编码目标运动图像的运动图像数，运动图像获取单元获取一个或多个编码目标运动图像，处理 方法指定单元根据获取的计数指定影响计算量的与编码处理相关的处理方法，编码处理单元对于所获取的一个或多个运动图像，当多个移动 图片是复数。 编码单元使用指定的方法进行编码处理。

公开(公告)号：US07949860B2

公开(公告)日：2011-05-24

申请号：US12093884

申请日：2006-11-21

申请人： Masaki Maeda ,  Hideshi Nishida ,  Yorihiko Wakayama

发明人： Masaki Maeda ,  Hideshi Nishida ,  Yorihiko Wakayama

IPC分类号： G06F7/38 ,  G06F15/00

CPC分类号： G06F15/7867

摘要： A processor according to the present invention cyclically executes a plurality of threads, for each time period allocated thereto. The processor stores, for each thread, configuration information of operation cells. Each of the threads (i) causes the execution of a different predetermined number of operation cells in series, and successively reconfigures an operation cell that has completed a last operation thereof in the time period allocated to a current thread, based on a stored piece of configuration information of the operation cell that corresponds to a next thread, and (ii) causes concurrent execution of an operation cell having a configuration for the current thread and an operation cell having a configuration for the next thread.

摘要翻译： 根据本发明的处理器在分配给它的每个时间段周期性地执行多个线程。 处理器为每个线程存储操作单元的配置信息。 每个线程（i）使得执行不同的预定数量的操作单元串联，并且在分配给当前线程的时间段内，基于存储的一段 与下一个线程对应的操作单元的配置信息，以及（ii）使具有当前线程的配置的操作单元和具有下一个线程的配置的操作单元的并发执行。

公开(公告)号：US20050216699A1

公开(公告)日：2005-09-29

申请号：US11054049

申请日：2005-02-09

申请人： Takeshi Tanaka ,  Hideshi Nishida ,  Masashi Hoshino ,  Takeshi Furuta

发明人： Takeshi Tanaka ,  Hideshi Nishida ,  Masashi Hoshino ,  Takeshi Furuta

IPC分类号： G06F9/318 ,  G06F9/38 ,  G06F15/00 ,  G06F15/80

CPC分类号： G06F9/3885 ,  G06F9/30181 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3828 ,  G06F9/3887 ,  G06F15/8015

摘要： A processor having a plurality of processing elements and a decoder operable to decode an instruction. Each of the plurality of processing elements includes: a transfer pattern storage unit operable to store a transfer pattern value that indicates a processing element from which data is transferred; a transfer unit operable to perform a data transfer from the processing element indicated by the transfer pattern value; and an update unit operable to update the transfer pattern value stored in the transfer pattern storage unit, in accordance with a result of decoding a latest instruction by the decoder.

摘要翻译： 具有多个处理元件的处理器和可解码指令的解码器。 多个处理元件中的每一个包括：传送图案存储单元，用于存储指示从其传送数据的处理元件的传送图案值; 传送单元，其可操作以从由所述传送图案值指示的处理单元执行数据传送; 以及更新单元，用于根据由解码器解码最新指令的结果来更新存储在传送模式存储单元中的传送模式值。

公开(公告)号：US20050182916A1

公开(公告)日：2005-08-18

申请号：US10949230

申请日：2004-09-27

申请人： Takahiro Kageyama ,  Hideshi Nishida ,  Takeshi Tanaka ,  Kouji Nakajima

发明人： Takahiro Kageyama ,  Hideshi Nishida ,  Takeshi Tanaka ,  Kouji Nakajima

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F9/34 ,  G06F9/45 ,  G06F15/00

CPC分类号： G06F9/3853 ,  G06F9/30145 ,  G06F9/30156 ,  G06F9/3016 ,  G06F9/3822 ,  G06F9/3885

摘要： A VLIW processor which has an instruction set whose size is reduced so that a small number of bits are necessary to specify registers is provided. The VLIW processor 10 comprises the register file 12, the first-the third operation units 14a-14c and the like, and executes the very long instruction word. And, the very long instruction word includes the register specifying field which specifies a least one of the registers in the register file 12 and a plurality of instructions. The operand of each instruction has the bits, src1 src2 and dst, indicating whether or not the registers specified by the register specifying field are to be used as the source register and the destination register.

摘要翻译： 提供了具有指令集的VLIW处理器，其大小被减小以便需要少量位来指定寄存器。 VLIW处理器10包括寄存器文件12，第一个第三操作单元14 a-14 c等，并且执行非常长的指令字。 并且，长指令字包括指定寄存器文件12中的至少一个寄存器的寄存器指定字段和多个指令。 每个指令的操作数都有位src 1 src 2和dst，表示由寄存器指定字段指定的寄存器是否用作源寄存器和目的寄存器。

公开(公告)号：US20050138326A1

公开(公告)日：2005-06-23

申请号：US11009056

申请日：2004-12-13

申请人： Kengo Terada ,  Takeshi Tanaka ,  Hideshi Nishida

发明人： Kengo Terada ,  Takeshi Tanaka ,  Hideshi Nishida

IPC分类号： G06F12/02 ,  G06F12/00 ,  G06F15/00 ,  G06F15/80 ,  G06T1/20

CPC分类号： G06T1/20 ,  G06F9/30181 ,  G06F9/345 ,  G06F9/3885 ,  G06F9/3887

摘要： A parallel operation apparatus of a SIMD type comprises a processor element group of the SIMD type including a plurality of processor elements, wherein the respective processor elements simultaneously execute an identical operation, a data memory accessible from the respective processor elements in the processor element group, and an address conversion unit for converting an address with respect to the data memory accessed by the processor elements in accordance with a control signal by changing bit positions of the address. The address conversion unit preferably rearranges a first bit, a second bit, and a third bit from a lower order of address data into the second bit, the third bit, and the first bit from the lower order in the change of the bit positions.

摘要翻译： SIMD类型的并行操作装置包括包括多个处理器元件的SIMD类型的处理器元件组，其中相应的处理器元件同时执行相同的操作，可从处理器元件组中的相应处理器元件访问的数据存储器， 以及地址转换单元，用于通过改变地址的位位置来根据控制信号转换相对于由处理器单元访问的数据存储器的地址。 地址转换单元优选地从比特位置的改变中的低阶地址将第一比特，第二比特和第三比特从地址数据的较低阶重新排列成第二比特，第三比特和第一比特。

公开(公告)号：US20090228691A1

公开(公告)日：2009-09-10

申请号：US11720899

申请日：2005-08-24

申请人： Takeshi Furuta ,  Hideshi Nishida ,  Takeshi Tanaka

发明人： Takeshi Furuta ,  Hideshi Nishida ,  Takeshi Tanaka

IPC分类号： G06F9/302

CPC分类号： G06F9/30094 ,  G06F9/30036 ,  G06F9/30058 ,  G06F9/30072 ,  G06F9/3885

摘要： An arithmetic processing apparatus capable of performing an arithmetic operation for generating a condition flag commonly referred to by using a condition flag generated on an arithmetic operation unit basis in as few steps as possible is provided. The arithmetic processing apparatus, which processes multiple data in parallel based on single instruction, includes: processing elements capable of performing a common arithmetic operation based on the evaluation result of the instruction stored in the instruction register; and a condition flag arithmetic operation unit capable of performing one of the logical operation and the comparison operation on the condition flag retained in each processing element, transferring the operation result to each processing element, and updating the condition flag based on the operation result.

摘要翻译： 提供一种算术处理装置，其能够以尽可能少的步长进行用于生成通常使用在算术运算单元上生成的条件标志共同参照的条件标志的算术运算。 基于单个指令并行处理多个数据的算术处理装置包括：能够基于存储在指令寄存器中的指令的评估结果执行公共算术运算的处理单元; 以及条件标志算术运算单元，其能够对保留在每个处理单元中的条件标志执行逻辑运算和比较运算中的一个，将运算结果传送给各处理单元，并根据运算结果更新条件标志。

公开(公告)号：US07412587B2

公开(公告)日：2008-08-12

申请号：US11054049

申请日：2005-02-09

申请人： Takeshi Tanaka ,  Hideshi Nishida ,  Masashi Hoshino ,  Takeshi Furuta

发明人： Takeshi Tanaka ,  Hideshi Nishida ,  Masashi Hoshino ,  Takeshi Furuta

IPC分类号： G06F9/30

CPC分类号： G06F9/3885 ,  G06F9/30181 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3828 ,  G06F9/3887 ,  G06F15/8015

摘要： A processor having a plurality of processing elements and a decoder operable to decode an instruction. Each of the plurality of processing elements includes: a transfer pattern storage unit operable to store a transfer pattern value that indicates a processing element from which data is transferred; a transfer unit operable to perform a data transfer from the processing element indicated by the transfer pattern value; and an update unit operable to update the transfer pattern value stored in the transfer pattern storage unit, in accordance with a result of decoding a latest instruction by the decoder.

摘要翻译： 具有多个处理元件的处理器和可解码指令的解码器。 多个处理元件中的每一个包括：传送图案存储单元，用于存储指示从其传送数据的处理元件的传送图案值; 传送单元，其可操作以从由所述传送图案值指示的处理单元执行数据传送; 以及更新单元，用于根据由解码器解码最新指令的结果来更新存储在传送模式存储单元中的传送模式值。