公开(公告)号：US20120038403A1

公开(公告)日：2012-02-16

申请号：US13190915

申请日：2011-07-26

申请人： Norihiko SATANI ,  Yuichi Matsushita ,  Takahiro Imayoshi

发明人： Norihiko SATANI ,  Yuichi Matsushita ,  Takahiro Imayoshi

IPC分类号： H03L7/00

CPC分类号： H03L9/00 ,  G09G3/3685 ,  G09G2370/08 ,  G09G2370/14

摘要： In a semiconductor circuit, a high frequency level detecting unit detects a level of a high frequency component adjusted with a first adjusting unit, and a first control unit controls a first gain of the adjusting unit according to the level of the high frequency component thus detected. Further, a low frequency level detecting unit detects a level of a low frequency component adjusted with a second adjusting unit. A second control unit controls a second gain according to the level of the high frequency component and the level of the low frequency component thus adjusted, so that a difference between the level of the high frequency component adjusted with the first adjusting unit and the level of the low frequency component adjusted with the second adjusting unit becomes smaller than a specific level determined in advance.

摘要翻译： 在半导体电路中，高频电平检测单元检测由第一调整单元调整的高频分量的电平，第一控制单元根据检测到的高频分量的电平来控制调整单元的第一增益 。 此外，低频电平检测单元检测由第二调整单元调整的低频分量的电平。 第二控制单元根据高频分量的电平和由此调整的低频分量的电平来控制第二增益，使得由第一调整单元调整的高频分量的电平与第一调整单元的电平之间的差 用第二调节单元调节的低频分量变得比预先确定的特定水平小。

公开(公告)号：US20060245783A1

公开(公告)日：2006-11-02

申请号：US11410965

申请日：2006-04-26

申请人： Naoya Kamimura ,  Yuichi Matsushita

发明人： Naoya Kamimura ,  Yuichi Matsushita

IPC分类号： G03G15/08

CPC分类号： G03G15/0898

摘要： A developer cartridge includes a developer roller, a support member and a first seal member. The developer roller has a rotational axis and a peripheral surface. The peripheral surface includes a center zone and an end zone at one end portion in an axial direction. The support member supports the developer roller to be rotatable about the rotational axis. The support member has an opposing surface opposed to the end zone. A protrusion protrudes from the opposing surface, and extends in a direction crossing with the axial direction. The first seal member is disposed between the end zone and the opposing surface in order to prevent developer from leaking out of a space formed between the end zone and the opposing surface.

摘要翻译： 显影剂盒包括显影辊，支撑构件和第一密封构件。 显影辊具有旋转轴和外周表面。 外周面在轴向的一端部包括中心区域和端部区域。 支撑构件支撑显影辊可围绕旋转轴线旋转。 支撑构件具有与端部区域相对的相对表面。 突起从相对的表面突出，并且沿与轴向交叉的方向延伸。 第一密封构件设置在端部区域和相对表面之间，以防止显影剂从端部区域和相对表面之间形成的空间泄漏出来。

公开(公告)号：US06693471B2

公开(公告)日：2004-02-17

申请号：US10252682

申请日：2002-09-24

申请人： Yuichi Matsushita

发明人： Yuichi Matsushita

IPC分类号： H03L700

CPC分类号： H03K17/223

摘要： A start-up circuit includes a power supply node which receives a power supply voltage, a ground node which receives a ground voltage, a first node, a first capacitor which is coupled between the first node and the ground node, a supply circuit which is coupled between the power supply node and the first node, and which supplies an electrical charge from the power supply node to the first capacitor, a discharge circuit which is coupled between the first node and the ground node, and which discharges an electrical charge stored in the first capacitor to the ground node, and an output circuit which is connected to the first node, and which outputs a start-up signal when a voltage level of the first node becomes higher than a set voltage level.

公开(公告)号：US06225853B1

公开(公告)日：2001-05-01

申请号：US09055999

申请日：1998-04-07

申请人： Yuichi Matsushita

发明人： Yuichi Matsushita

IPC分类号： G05F110

CPC分类号： H02M3/073

摘要： A booster circuit uses a source voltage to generate a boosted voltage that is higher than the source voltage. The booster circuit has two capacitors. The two capacitors are alternately charged and discharged in response to a signal applied to an input terminal. The first capacitor is discharged to boost a voltage at the boosting node, whereas the second capacitor is discharged to boost the voltage at an output terminal. Further, the booster circuit includes a control circuit. When the voltage at the input terminal changes from an “H” level to an “L” level, the control circuit supplies a voltage for discharging the first capacitor to the first capacitor after the second capacitor has been brought into a charging state. Since the voltage at the output terminal is reduced by the charging of the second capacitor, a transistor is deactivated in response to the voltage at the output terminal. As a result, the boosting node and the source voltage can be prevented from being coupled by the transistor. The voltage at the boosting node is boosted by the discharge of the first capacitor, and the output terminal and the source voltage are coupled by a transistor that is activated in response to the boosted voltage at the boosting node. It is thus possible to increase the voltage at the output terminal to the source voltage VCC.

摘要翻译： 升压电路使用源极电压来产生高于源极电压的升压电压。 升压电路有两个电容。 响应于施加到输入端子的信号，两个电容器被交替地充电和放电。 第一电容器被放电以升高升压节点处的电压，而第二电容器被放电以升高输出端子处的电压。 此外，升压电路包括控制电路。 当输入端子的电压从“H”电平变为“L”电平时，控制电路在第二电容器进入充电状态之后，向第一电容器提供用于将第一电容器放电的电压。 由于通过第二电容器的充电来减小输出端子处的电压，所以晶体管响应于输出端子处的电压被去激活。 结果，可以防止升压节点和源电压被晶体管耦合。 升压节点处的电压通过第一电容器的放电而升高，并且输出端子和源极电压通过响应于升压节点处的升压电压而被激活的晶体管耦合。 因此可以将输出端子处的电压增加到源极电压VCC。

公开(公告)号：US6084815A

公开(公告)日：2000-07-04

申请号：US241414

申请日：1999-02-02

申请人： Yuichi Matsushita ,  Kenji Satou

发明人： Yuichi Matsushita ,  Kenji Satou

IPC分类号： G11C29/04 ,  G11C29/00 ,  G11C7/00

CPC分类号： G11C29/785 ,  G11C29/80

摘要： A semiconductor device includes plural fuse wiring paths which extend substantially parallel to each other in a first direction, each of the fuse wiring paths having a fuse element. A normal column line extends in a second direction substantially perpendicular to the first direction, the normal column line corresponding to a normal memory cell which stores data. The semiconductor memory device further includes a redundant column line extending in the second direction, the redundant column line corresponding to a redundant memory cell which stores data. A logic circuit receives respective signals on the plural fuse wiring paths, and outputs a selection signal according to these signals. The semiconductor device also includes a switching circuit coupled between the logic circuit and the normal and redundant column lines, which receives an address signal and the selection signal, and which selectively transfers the address signal to the normal column line or the redundant column line in response to the selection signal.

摘要翻译： 半导体器件包括在第一方向上基本上彼此平行延伸的多个熔丝布线路径，每个熔丝布线路径具有熔丝元件。 正常列线在基本上垂直于第一方向的第二方向上延伸，正常列线对应于存储数据的常规存储器单元。 半导体存储器件还包括沿第二方向延伸的冗余列线，冗余列线对应于存储数据的冗余存储器单元。 逻辑电路接收多个熔丝布线路径上的相应信号，并根据这些信号输出选择信号。 半导体器件还包括耦合在逻辑电路和正常冗余列线之间的开关电路，其接收地址信号和选择信号，并且响应地选择性地将地址信号传送到正常列线或冗余列线 到选择信号。

公开(公告)号：US6072736A

公开(公告)日：2000-06-06

申请号：US418021

申请日：1999-10-14

申请人： Kenji Sato ,  Yuichi Matsushita

发明人： Kenji Sato ,  Yuichi Matsushita

IPC分类号： G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/78

摘要： There is provided a semiconductor memory device 100 comprising memory cell blocks 20-1 to 20-n, decoder circuits 10-1 to 10-n that carry out the redundant operation provided so as to correspond to each memory cell block, a Roll Call signal transmission circuit 110 which detect if the redundant function is in operation; wherein each decoder circuit outputs a decoder signal FCi at low level to the Roll Call signal transmission circuit when the redundant function is in operation, but outputs a decoder signal at high level when the redundant function is not in operation, and wherein the Roll Call signal transmission circuit outputs a judgment signal at high level when all the decoder signals are at high level, but outputs a low level judgment signal when any of the decoder signals is at low level.

摘要翻译： 提供了包括存储单元块20-1至20-n的半导体存储器件100，执行提供以对应于每个存储器单元块的冗余操作的解码器电路10-1至10-n，滚动呼叫信号 发送电路110，检测冗余功能是否正在运行; 其中当所述冗余功能处于工作状态时，每个解码器电路将低信号译码器信号FCi输出到所述滚动呼叫信号传输电路，但当所述冗余功能不工作时，输出解码器信号为高电平，并且其中所述滚动呼叫信号 当所有解码器信号处于高电平时，发送电路输出高电平的判断信号，而当解码器信号为低电平时输出低电平判断信号。

公开(公告)号：US5877650A

公开(公告)日：1999-03-02

申请号：US637621

申请日：1996-04-29

申请人： Yuichi Matsushita

发明人： Yuichi Matsushita

IPC分类号： H01L27/04 ,  G11C11/407 ,  H01L21/822 ,  H02M3/07 ,  G05F1/10

CPC分类号： H02M3/073

摘要： A booster circuit uses a source voltage to generate a boosted voltage that is higher than the source voltage. The booster circuit has two capacitors. The two capacitors are alternately charged and discharged in response to a signal applied to an input terminal. The first capacitor is discharged to boost the voltage at the boosting node, whereas the second capacitor is discharged to boost the voltage at an output terminal. Further, the booster circuit includes a control circuit. When the voltage at the input terminal changes from an "H" level to an "L" level, the control circuit supplies a voltage for discharging the first capacitor to the first capacitor after the second capacitor has been brought into a charging state. Since the voltage at the output terminal is reduced by the charging of the second capacitor, a transistor is deactivated in response to the voltage at the output terminal. As a result, the boosting node and the source voltage can be prevented from being coupled by the transistor. The voltage at the boosting node is boosted by the discharge of the first capacitor, and the output terminal and the source voltage are coupled by a transistor that is activated in response to the boosted voltage at the boosting node. It is thus possible to increase the voltage at the output terminal to the source voltage V.sub.CC.

摘要翻译： PCT No.PCT / JP95 / 10770 Sec。 371日期：1996年4月29日 102（e）日期1996年4月29日PCT提交1995年9月6日PCT公布。 出版物WO96 / 08070 日期1996年3月14日升压电路使用源电压产生高于源极电压的升压电压。 升压电路有两个电容。 响应于施加到输入端子的信号，两个电容器被交替地充电和放电。 第一电容器被放电以升高升压节点处的电压，而第二电容器被放电以升高输出端子处的电压。 此外，升压电路包括控制电路。 当输入端子的电压从“H”电平变为“L”电平时，控制电路在第二电容器进入充电状态之后，向第一电容器提供用于将第一电容器放电的电压。 由于通过第二电容器的充电来减小输出端子处的电压，所以晶体管响应于输出端子处的电压被去激活。 结果，可以防止升压节点和源电压被晶体管耦合。 升压节点处的电压通过第一电容器的放电而升高，并且输出端子和源极电压通过响应于升压节点处的升压电压而被激活的晶体管耦合。 因此可以将输出端子处的电压增加到源极电压VCC。

公开(公告)号：US5801999A

公开(公告)日：1998-09-01

申请号：US769158

申请日：1996-12-18

申请人： Kenji Satou ,  Yuichi Matsushita

发明人： Kenji Satou ,  Yuichi Matsushita

IPC分类号： G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/808 ,  G11C29/848

摘要： A redundant semiconductor memory capable of functioning normally on the whole even if two column (or row) lines do not function normally. The semiconductor memory includes primary and secondary selection circuits, primary and secondary switchover circuits, and (N+2) memory cell groups. The primary switchover circuit receives a decoded address signal of N bits for selecting one memory sell group, and outputs to the secondary switchover circuit a signal of (N+1) bits which is generated by inserting a bit into a position of the inputted decoded address signal specified by the primary selection circuit. The secondary switchover circuit outputs to the memory cell groups a signal of (N+2) bits which is generated by inserting a bit into a position of the inputted signal specified by the secondary selection circuit.

摘要翻译： 即使两列（或行）线路不能正常工作，也能够在整体上正常工作的冗余半导体存储器。 半导体存储器包括主要和次要选择电路，主要和次要切换电路和（N + 2）个存储器单元组。 主切换电路接收用于选择一个存储器销售组的N位的解码地址信号，并且向副切换电路输出通过将位插入到输入的解码地址的位置而生成的（N + 1）位的信号 信号由主选择电路指定。 二次切换电路向存储器单元输出通过将位插入到由次级选择电路指定的输入信号的位置而产生的（N + 2）位的信号。

公开(公告)号：US5365488A

公开(公告)日：1994-11-15

申请号：US70239

申请日：1993-06-02

申请人： Yuichi Matsushita

发明人： Yuichi Matsushita

IPC分类号： G11C11/409 ,  G11C7/10 ,  G11C7/00

CPC分类号： G11C7/1048

摘要： A data reading circuit of the present invention comprises a pair of data buses supplied with complementary potentials respectively, a first reference voltage source having a first potential, a second reference voltage source having a second potential, a first switch connected to the first reference voltage source and the pair of data buses and responsive to a first clamping signal thereby to electrically connect the first reference voltage source to the pair of data buses, and a second switch connected to the second reference voltage source and the pair of data buses and responsive to a second clamping signal thereby to electrically connect the second reference voltage source to the pair of data buses.

摘要翻译： 本发明的数据读取电路分别包括互补电位的一对数据总线，具有第一电位的第一参考电压源，具有第二电位的第二参考电压源，连接到第一参考电压源的第一开关 和一对数据总线，并且响应于第一钳位信号，从而将第一参考电压源电连接到该对数据总线，以及连接到第二参考电压源和一对数据总线的第二开关，并响应于 第二钳位信号从而将第二参考电压源电连接到该对数据总线。

公开(公告)号：US09146494B2

公开(公告)日：2015-09-29

申请号：US14039815

申请日：2013-09-27

申请人： Yuichi Matsushita

发明人： Yuichi Matsushita

IPC分类号： G03G15/06

CPC分类号： G03G15/065

摘要： An image forming apparatus includes a charging member for charging a surface of a photosensitive member to a first potential, an exposing member for partially exposing the charged surface of the photosensitive member such that a potential of the exposed portions becomes a second potential smaller than the first potential, a developer carrier for feeding developer onto the photosensitive member, a discharging-beam member for irradiating a discharging beam onto the photosensitive member having a developer image, and a control device configured to: control a developing bias to become a third potential larger than the second potential and smaller than the first potential; and control a discharging bias such that a potential of portions on the photosensitive member where the developer image has not been formed becomes a fourth potential not smaller than the third potential and smaller than the first potential.

摘要翻译： 图像形成装置包括用于将感光构件的表面充电到第一电位的充电构件，用于部分地曝光感光构件的带电表面的曝光构件，使得暴露部分的电位变得比第一电位小的第二电位 用于将显影剂供给到感光构件上的显影剂载体，用于将放电束照射到具有显影剂图像的感光构件上的放电梁构件，以及控制装置，其被配置为：将显影偏压控制为大于 第二个潜力小于第一个潜力; 并且控制放电偏压，使得未形成显影剂图像的感光构件上的部分的电位成为不小于第三电位且小于第一电位的第四电位。