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公开(公告)号：US4521704A
公开(公告)日：1985-06-04
申请号：US462204
申请日：1983-01-31
IPC分类号： G11C11/417 , H03F3/26 , H03F3/45 , H03K5/02
CPC分类号： H03F3/265 , H03F3/45076 , H03F2203/45318 , H03F2203/45394
摘要： A differential amplifying circuit includes a pair of main amplifying circuits (5a, 5b) each having at least three input terminals and at least one output terminal, and a pair of auxiliary amplifying circuits (6a, 6b) each having at least one input terminal. Complimentary inputs (D1, D1) are connected to the input terminals of said pair of auxiliary amplifying circuits (6a, 6b), the outputs (D2, D2) of the main amplifying circuits (5a, 5b) are connected as crossing feedback inputs to at least a pair of input terminals of said pair of main amplifying circuits (5a, 5b), the complimentary inputs (D2, D2) are also connected to the other at least one pair of input terminals, and the outputs of said auxiliary amplifying circuits (6a, 6b) are further connected to the further at least pair of input terminals.
摘要翻译： 差分放大电路包括一对主放大电路（5a，5b），每一个具有至少三个输入端和至少一个输出端，以及一对辅助放大电路（6a，6b），每一个具有至少一个输入端。 免费输入（D1，＆amp; upbar＆D）连接到所述一对辅助放大电路（6a，6b）的输入端，主放大电路（5a，5b）的输出（D2，＆amp; upbar＆D） 输入到所述一对主放大电路（5a，5b）中的至少一对输入端，所述互补输入（D2，＆amp;上和下）也连接到另一个至少一对输入端，并且所述输出 辅助放大电路（6a，6b）进一步连接到另外的至少一对输入端。
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公开(公告)号：US20090034620A1
公开(公告)日：2009-02-05
申请号：US12088303
申请日：2006-06-29
申请人： Mayumi Okumura , Masaki Hamamoto , Yuichiro Murachi , Junichi Miyakoshi , Masahiko Yoshimoto , Tetsuro Matsuno
发明人： Mayumi Okumura , Masaki Hamamoto , Yuichiro Murachi , Junichi Miyakoshi , Masahiko Yoshimoto , Tetsuro Matsuno
IPC分类号： H04N7/26
CPC分类号： H04N19/53
摘要： A motion estimation method capable of reducing the amount of calculation as compared to a full search method. In the method, a coarse search block and fine search blocks are defined. The fine search blocks are given by dividing the coarse search block into a plurality of blocks so that the fine search blocks are contained in the coarse search block. A sparsely interpolated image and a densely interpolated image are defined. A first search is performed using the defined coarse search block and the defined sparsely interpolated image. A second search is performed using the defined coarse search block and the defined densely interpolated image. With regard to search blocks belonging to the fine search blocks, only a surrounding region of an optimal point obtained in the first search is searched.
摘要翻译： 一种与全搜索方法相比能够减少计算量的运动估计方法。 在该方法中，定义了粗搜索块和精细搜索块。 精细搜索块通过将粗略搜索块划分成多个块来给出，使得精细搜索块被包含在粗略搜索块中。 定义了稀疏内插图像和密集内插图像。 使用定义的粗略搜索块和定义的稀疏内插图像来执行第一搜索。 使用定义的粗略搜索块和所定义的密集内插图像来执行第二次搜索。 关于属于精细搜索块的搜索块，仅搜索在第一搜索中获得的最佳点的周围区域。
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43.发明授权公开(公告)号：US06237023B1
公开(公告)日：2001-05-22
申请号：US08873104
申请日：1997-06-11
申请人： Masahiko Yoshimoto
发明人： Masahiko Yoshimoto
IPC分类号： G06F1516
CPC分类号： H04L63/102
摘要： When a server receives a service request from a client, identifiers of a terminal and of a user are acquired from the service request and authority with respect to the service request is uniquely decided from the terminal and user identifiers acquired. It is then determined, using the authority decided, whether or not to accept the service request.
摘要翻译： 当服务器从客户端接收到服务请求时，从服务请求获得终端和用户的标识符，并且从终端和所获得的用户标识符唯一地确定关于服务请求的权限。 然后，使用所决定的权限确定是否接受服务请求。
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44.发明授权Selectively processing plurality of transactions using transaction identifiers that including committing, aborting updating and continuous updating content in a plurality of shared data 失效使用包括在多个共享数据中提交，中止更新和连续更新内容的事务标识符来选择性地处理多个事务
公开(公告)号：US6148299A
公开(公告)日：2000-11-14
申请号：US873712
申请日：1997-06-12
申请人： Masahiko Yoshimoto
发明人： Masahiko Yoshimoto
CPC分类号： G06F9/466 , Y10S707/99938 , Y10S707/99953
摘要： An information processing apparatus manages the correspondence between identification information, which is for identifying a plurality of transactions within one process, and the transactions. To this end, the information processing apparatus operates on the identification information by operations including creation, cancellation and switching of the identification information. The creation, cancellation and switching of the identification information then results in the corresponding operation on the respective transaction.
摘要翻译： 信息处理装置管理用于识别一个进程内的多个事务的识别信息与事务之间的对应关系。 为此，信息处理装置通过包括识别信息的创建，取消和切换的操作对识别信息进行操作。 识别信息的创建，取消和切换导致相应的交易的相应操作。
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公开(公告)号：US5394355A
公开(公告)日：1995-02-28
申请号：US109509
申请日：1993-08-20
CPC分类号： G11C11/56 , G11C11/5692 , G11C2211/5617 , G11C2211/5634
摘要： A read only memory includes a memory cell provided at an intersection between a word line and a bit line, and a plurality of reference potential transmission lines each receiving a reference potential determined in accordance with an externally applied potential designating signal. The memory cell includes a transistor element having a gate coupled to a word line, a drain coupled to a bit line and a source which is coupled to one of the reference potential transmission lines or is held in an open state. Stored data in the memory cell is changed by switching the potentials of the reference potential transmission lines. This enables storing of different data bits in one memory cell.
摘要翻译： 只读存储器包括提供在字线和位线之间的交叉点处的存储单元和多个参考电位传输线，每个参考电位传输线接收根据外部施加的电位指定信号确定的参考电位。 存储单元包括晶体管元件，其具有耦合到字线的栅极，耦合到位线的漏极和耦合到参考电位传输线中的一个或保持在打开状态的源极。 通过切换参考电位传输线的电位来改变存储单元中的存储数据。 这使得能够将不同的数据位存储在一个存储单元中。
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公开(公告)号：US4961169A
公开(公告)日：1990-10-02
申请号：US137145
申请日：1987-12-23
CPC分类号： H04N5/907 , G11C19/00 , G11C7/1006
摘要： A variable length shift register comprises a memory cell array (1) having memory cells arranged in a matrix of row and columns, a variable length ring pointer (2) responsive to a bit length selecting signal for sequentially activating a single row in the memory cell array in a recirculated manner within a predetermined constant range, an input buffer (4) for writing data into a memory cell of the activated row, and an output buffer (5) for reading out data from a memory cell of the activated row.
摘要翻译： 可变长度移位寄存器包括具有以行和列的矩阵排列的存储器单元的存储单元阵列（1），响应于位长选择信号的可变长度环形指针（2），用于顺序地激活存储单元中的单个行 在预定的恒定范围内以再循环的方式排列阵列，用于将数据写入激活的行的存储单元的输入缓冲器（4），以及用于从所激活的行的存储单元读出数据的输出缓冲器（5）。
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公开(公告)号：US4876610A
公开(公告)日：1989-10-24
申请号：US137439
申请日：1987-12-23
CPC分类号： H04N1/52 , G06K9/38 , H04N1/4052 , G06K2209/01
摘要： An image processing apparatus for digitizing an analog image by dispersing the digitizing error to the surrounding areas. The characteristics or edge of the analog image are identified, and the error dispersing area is varied according to the result of identification, thus enabling reproduction of the image with high quality regardless of the nature of the original image.
摘要翻译： 一种图像处理装置，用于通过将数字化误差分散到周围区域来数字化模拟图像。 识别模拟图像的特征或边缘，并且根据识别结果改变误差分散区域，从而能够以高质量再现图像，而与原始图像的性质无关。
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公开(公告)号：US4849937A
公开(公告)日：1989-07-18
申请号：US169066
申请日：1988-03-17
申请人： Masahiko Yoshimoto
发明人： Masahiko Yoshimoto
CPC分类号： H04N5/907 , G11C7/00 , G11C7/1042 , G11C7/1075 , G11C8/04
摘要： A first memory cell array (84) has an even address space and a second memory cell array 94 has an odd address space. The memory cell arrays (84, 94) are alternately accessed by even address signals generated from an address counter (81) and odd address signals generated from an address counter (91) so that the data stored in the memory cell arrays are alternately read while new input data are written in the accessed memory cells.
摘要翻译： 第一存储单元阵列（84）具有偶数地址空间，第二存储单元阵列94具有奇数地址空间。 存储单元阵列（84,94）由从地址计数器（81）产生的偶数地址信号和从地址计数器（91）产生的奇数地址信号交替访问，使得存储在存储单元阵列中的数据被交替地读取， 新的输入数据被写入访问的存储单元。
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公开(公告)号：US4606013A
公开(公告)日：1986-08-12
申请号：US579604
申请日：1984-02-13
申请人： Masahiko Yoshimoto
发明人： Masahiko Yoshimoto
CPC分类号： G11C29/789 , G11C29/832
摘要： A redundancy-secured semiconductor memory including a matrix of regular memory cells consisting of a plurality of regular memory cell trains, an extra memory cell train for redundant construction, and a taking-over system for enabling the extra memory cell train to take over the function of a faulty regular memory cell train including a faulty bit, wherein the taking-over system comprises a decoder and a monostable latching circuit connected to the decoder through a current conducting element capable of breakage in response to when one of the regular memory cell trains comes to include a faulty bit, thereby enabling the monostable latching circuit to fix its output to the low logic potential. Thus, the faulty regular memory cell train is kept in an unselected state without DC power consumption.
摘要翻译： 一种冗余保护半导体存储器，包括由多个常规存储单元列组成的常规存储器单元矩阵，用于冗余结构的额外存储单元串，以及用于使额外存储单元串能够接管功能的接管系统 包括故障位的故障常规存储器单元串，其中，所述接收系统包括解码器和单稳态锁存电路，所述解调器和单稳态锁存电路通过电流传导元件连接到所述解码器，所述电流导电元件响应于当所述常规存储器单元列中的一个来自 以包括故障位，从而使单稳态锁存电路将其输出固定为低逻辑电位。 因此，故障的常规存储器单元串在没有DC功率消耗的情况下保持在未选择状态。
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