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公开(公告)号：US5289406A
公开(公告)日：1994-02-22
申请号：US744098
申请日：1991-08-13
CPC分类号： G11C11/56 , G11C11/5692 , G11C2211/5617 , G11C2211/5634
摘要： A read only memory includes a memory cell provided at an intersection between a word line and a bit line, and a plurality of reference potential transmission lines each receiving a reference potential determined in accordance with an externally applied potential designating signal. The memory cell includes a transistor element having a gate coupled to a word line, a drain coupled to a bit line and a source which is coupled to one of the reference potential transmission lines or is held in an open state. Stored data in the memory cell is changed by switching the potentials of the reference potential transmission lines. This enables storing of different data bits in one memory cell.
摘要翻译： 只读存储器包括提供在字线和位线之间的交叉点处的存储单元和多个参考电位传输线，每个参考电位传输线接收根据外部施加的电位指定信号确定的参考电位。 存储单元包括晶体管元件，其具有耦合到字线的栅极，耦合到位线的漏极和耦合到参考电位传输线中的一个或保持在打开状态的源极。 通过切换参考电位传输线的电位来改变存储单元中的存储数据。 这使得能够将不同的数据位存储在一个存储单元中。
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公开(公告)号：US5394355A
公开(公告)日：1995-02-28
申请号：US109509
申请日：1993-08-20
CPC分类号： G11C11/56 , G11C11/5692 , G11C2211/5617 , G11C2211/5634
摘要： A read only memory includes a memory cell provided at an intersection between a word line and a bit line, and a plurality of reference potential transmission lines each receiving a reference potential determined in accordance with an externally applied potential designating signal. The memory cell includes a transistor element having a gate coupled to a word line, a drain coupled to a bit line and a source which is coupled to one of the reference potential transmission lines or is held in an open state. Stored data in the memory cell is changed by switching the potentials of the reference potential transmission lines. This enables storing of different data bits in one memory cell.
摘要翻译： 只读存储器包括提供在字线和位线之间的交叉点处的存储单元和多个参考电位传输线，每个参考电位传输线接收根据外部施加的电位指定信号确定的参考电位。 存储单元包括晶体管元件，其具有耦合到字线的栅极，耦合到位线的漏极和耦合到参考电位传输线中的一个或保持在打开状态的源极。 通过切换参考电位传输线的电位来改变存储单元中的存储数据。 这使得能够将不同的数据位存储在一个存储单元中。
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3.发明授权Semiconductor integrated circuit device having a memory and an operational unit integrated therein 失效具有集成在其中的存储器和操作单元的半导体集成电路器件
公开(公告)号：US5379257A
公开(公告)日：1995-01-03
申请号：US767767
申请日：1991-09-30
IPC分类号： G11C11/41 , G11C7/10 , G11C11/401 , G11C13/00
CPC分类号： G11C7/1006 , G11C2207/104
摘要： A semiconductor integrated circuit device includes a memory cell array for storing data to be processed, and an operational unit for effecting a predetermined operation on the data read from the memory cell array. The memory cell array has first and second regions for storing first and second data words of first and second groups. The first data words and second data words each include a plurality of data bits. The first region includes a plurality of bit arrays for storing data bits of the same digit in the first data words, and the second region includes a plurality of bit arrays for storing data bite of the same digit in the second data words. The bit arrays of the first and second groups are arranged alternately in the order of digits of the data words. The bit arrays storing the data bits of the same digit form one subarray. The data bits in one data word are stored in the same positions of the bit arrays. The operational unit includes operational circuits each corresponding to one of the subarrays. Each operational circuit effects the predetermined operation on the data read from the two bit arrays in the corresponding subarray. Each bit array has selectors responsive to external addresses to select one column from each bit array and connect this column to a corresponding operational circuit.
摘要翻译： 半导体集成电路装置包括用于存储要处理的数据的存储单元阵列和用于对从存储单元阵列读取的数据进行预定操作的操作单元。 存储单元阵列具有用于存储第一和第二组的第一和第二数据字的第一和第二区域。 第一数据字和第二数据字各自包括多个数据位。 第一区域包括用于存储第一数据字中相同数位的数据位的多个位阵列，并且第二区域包括用于存储第二数据字中相同数字的数据位的多个位数组。 第一组和第二组的位阵列以数据字的数位顺序交替排列。 存储相同数位数据位的位数组形成一个子阵列。 一个数据字中的数据位存储在位阵列的相同位置。 操作单元包括各自对应于一个子阵列的操作电路。 每个操作电路对从相应子阵列中的两个位阵列读取的数据执行预定的操作。 每个位阵列具有响应于外部地址的选择器，从每个位阵列中选择一个列，并将该列连接到相应的运算电路。
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4.发明授权Semiconductor memory device usable as static type memory and read-only memory and operating method therefor 失效半导体存储器件可用作静态存储器和只读存储器及其操作方法
公开(公告)号：US5365475A
公开(公告)日：1994-11-15
申请号：US747204
申请日：1991-08-19
IPC分类号： G11C11/41 , G11C5/14 , G11C11/00 , G11C11/412 , G11C14/00
CPC分类号： G11C5/14 , G11C11/005 , G11C11/412
摘要： Each of memory cells of a semiconductor memory device comprises a transistor connected between a node and a node, a transistor connected between the node and a node, a transistor connected between a node and a node, and a transistor connected between node and a node. Each of the nodes is connected to either of a first potential line and a second supply line in a program unit when it is manufactured, and each of the nodes is connected to either of the first and the second ground lines in a program unit when it is manufactured.A supply potential is supplied to the first supply line, and the supply potential or the ground potential is selectively supplied to the second supply line. The ground potential is supplied to the first ground line, and the ground potential or the supply potential is selectively supplied to the second ground line.
摘要翻译： 半导体存储器件的每个存储单元包括连接在节点和节点之间的晶体管，连接在节点和节点之间的晶体管，连接在节点和节点之间的晶体管，以及连接在节点和节点之间的晶体管。 当制造节点时，每个节点在节目单元中连接到第一电位线和第二电源线中的任一个，并且当节点单元中的每个节点连接到节目单元中的任一个时 被制造。 电源电位被提供给第一电源线，并且电源电位或接地电位被选择性地提供给第二电源线。 接地电位被提供给第一接地线，并且接地电位或供电电势被选择性地提供给第二接地线。
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公开(公告)号：US4924314A
公开(公告)日：1990-05-08
申请号：US94648
申请日：1987-09-09
CPC分类号： H04N17/00
摘要： An integrated circuit 1 for video signal processing includes a 2-line memory 3, a video signal processing circuit 4 and a coincidence circuit 6. A digital video signal of 8 bits inputted to an input terminal group 2 is applied to the 2-line memory 3 and the coincidence circuit 6. Also, the 2-line delay signal of 8 bits outputted from the 2-line memory 3 is applied to the coincidence circuit 6. The coincidence circuit 6 determines coincidence or non-coincidence of the input digital video signal and the 2-line delay signal received and outputs the result of that determination through a coincidence output terminal. As a result, an operation of the 2-line memory 3 can be tested individually.
摘要翻译： 用于视频信号处理的集成电路1包括2行存储器3，视频信号处理电路4和符合电路6.输入到输入端子组2的8位数字视频信号被施加到2行存储器 此外，从2行存储器3输出的8位的2行延迟信号被施加到符合电路6.符合电路6确定输入数字视频信号的一致或非重合 并且接收到2行延迟信号，并通过一致输出端输出该确定的结果。 结果，可以单独测试2行存储器3的操作。
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公开(公告)号：US5093724A
公开(公告)日：1992-03-03
申请号：US494073
申请日：1990-03-15
CPC分类号： H04N17/00
摘要： An integrated circuit 1 for video signal processing comprises a 2-line memory 3, a video signal processing circuit 4 and a coincidence circuit 6. A digital video signal of 8 bits inputted to an input terminal group 2 is applied to the 2-line memory 3 and the coincidence circuit 6. Also, the 2-line delay signal of 8 bits outputted from the 2-line memory 3 is applied to the coincidence circuit 6. The coincidence circuit 6 determines coincidence or non-coincidence of the input digital video signal and the 2-line delay signal received and outputs the result of that determination through a coincidence output terminal. As a result, an operation of the 2-line memory 3 can be tested individually.
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7.发明授权Serial access memory device capable of controlling order of access to memory cell areas 失效能够控制访问存储单元区域的顺序的串行存取存储器件
公开(公告)号：US5633829A
公开(公告)日：1997-05-27
申请号：US739786
申请日：1991-07-31
摘要： A serial access memory device is disclosed in which order of access to writing and reading memory cell columns can be controlled. A writing column selecting circuit and a reading column selecting circuit are each comprised of ring pointers with a controllable number of stages. The number of stages of the ring pointers is controlled in response to control signals stored in a serial interface circuit. As a result, two ring pointers each having two stages are formed in the writing column selecting circuit while one ring pointer having four stages is formed in the reading column selecting circuit. After two data signals are written in selected two memory cell columns in parallel, written data signals are read out from serially selected four memory cell columns at a speed twice that in the writing. This serial access memory device is applied to a progressive scan conversion circuit for video signal processing.
摘要翻译： 公开了可以控制对写入和读取存储单元列的存取顺序的串行存取存储器件。 写入列选择电路和读取列选择电路各自包括具有可控级数的环形指针。 响应于存储在串行接口电路中的控制信号来控制环形指针的级数。 结果，在写入列选择电路中形成两个具有两级的环形指针，同时在读取列选择电路中形成具有四级的一个环形指针。 在两个数据信号并行写入所选择的两个存储单元列之后，以写入的两倍的速度从串行选择的四个存储单元列中读出写入的数据信号。 该串行访问存储器件被应用于用于视频信号处理的逐行扫描转换电路。
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公开(公告)号：US5029141A
公开(公告)日：1991-07-02
申请号：US322843
申请日：1989-03-14
IPC分类号： G11C11/401 , G11C7/00 , G11C7/10 , G11C8/02 , G11C11/405 , G11C11/407 , G11C11/4096 , G11C11/41
CPC分类号： G11C7/10 , G11C11/4096
摘要： The dynamic semiconductor memory device comprises a plurality of write block selecting lines and a plurality of read block selecting lines for selecting any one of the memory cell groups, a plurality of write row selecting lines for selecting any memory cells for a word in one of the memory cell groups selected by the write block selecting lines, a purality of first logic gates connected at one input terminals thereof to the write block selecting lines and at the other input terminals thereof to the write row selecting lines, a plurality of divisional write word lines each connecting an output terminal of one of the first logic gates in parallel to the corresponding memory cells for a word, a plurality of read row selecting lines for selecting any memory cells for a word in one of the memory cell groups selected by the read block selecting lines, a plurality of second logic gates connected at one input terminals thereof to the read block selecting lines and at the other input terminals thereof to the read row selecting lines, and a plurality of divisional read word lines each connecting an output terminal of one of the second logic gates in parallel to the corresponding memory cells for a word.
摘要翻译： 动态半导体存储器件包括多个写入块选择线和用于选择存储单元组中的任一个的多个读取块选择线，多个写入行选择线，用于选择任意一个字中的一个字的任何存储器单元 由写入块选择线选择的存储单元组，将其一个输入端连接到写入块选择线的多个第一逻辑门，并将其它输入端连接到写入行选择线;多个分开的写入字线 每个连接第一逻辑门之一的输出端并行地与一个字的对应的存储单元相连;多个读行选择线，用于选择由读块选择的一个存储单元组中的单词的任何存储单元 选择线，在其一个输入端连接到读取块选择线和其他输入端的多个第二逻辑门 以及多个分割读取字线，每个分割读取字线将一个第二逻辑门的输出端子并行连接到一个字的对应的存储器单元。
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9.发明授权Semiconductor memory device having redundancy and capable of sequentially selecting memory cell lines 失效半导体存储器件具有冗余并且能够顺序地选择存储器单元线
公开(公告)号：US5053999A
公开(公告)日：1991-10-01
申请号：US500328
申请日：1990-03-28
摘要： First-In First-Out (FIFO) memory device is disclosed. A ring pointer circuit sequentially and repeatedly selects memory cells in a memory cell array. When it is detected that a defective memory cell exists on a memory cell row, selection of that memory cell row is invalidated by the ring pointer circuit by cutting off a laser trimming line. In addition, by selectively cutting off laser trimming lines in a switching circuit and a redundancy ring pointer circuit, a redundancy memory cell row is selectively added in place of the defective memory cell row. Accordingly, stages required for the ring pointer circuit are maintained. In other words, the FIFO memory device having a defective memory cell is saved, resulting in improvement in yield in the manufacture.
摘要翻译： 先进先出（FIFO）存储器件被公开。 环形指针电路依次重复地选择存储单元阵列中的存储单元。 当检测到存储单元行中存在有缺陷的存储单元时，通过切断激光修整线，通过环形指针电路对该存储单元行的选择无效。 此外，通过选择性地切断开关电路和冗余环形指针电路中的激光微调线，选择性地添加冗余存储单元行来代替有缺陷的存储单元行。 因此，保持环形指针电路所需的阶段。 换句话说，具有缺陷存储单元的FIFO存储器件被保存，从而提高了制造中的产量。
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10.发明授权Semiconductor memory device having three-transistor type memory cells structure without additional gates 失效具有三晶体管型存储单元的半导体存储器件结构而没有附加栅极
公开(公告)号：US4935896A
公开(公告)日：1990-06-19
申请号：US266057
申请日：1988-11-02
IPC分类号： G11C7/06 , G11C11/405 , G11C11/406
CPC分类号： G11C7/065 , G11C11/405 , G11C11/406 , G11C7/067
摘要： A memory cell array (61) comprises a plurality of three-transistor type memory cells (10) arranged in a plurality of rows and columns. A plurality of pairs of write bit lines (WB1, WB2) and a plurality of read bit lines (RB) are provided corresponding to each column of the memory cell array (61). The plurality of write word lines (WWL) and the plurality of read word lines (RWL) are provided corresponding to each row of the memory cell array (61). Information is written to memory cells (10) in odd rows through the respective one write bit lines of the pairs of write bit lines (WB1, WB2), and information is written to memory cells (10) in even rows through the respective other write bit lines of the pairs of write bit lines (WB1, WB2). A sense amplifier (30) is connected to each of the pairs of write bit lines (WB1, WB2). At the time of write operation, refresh operation is performed by the sense amplifier (30) with respect to memory cells (10) in non-selected columns.
摘要翻译： 存储单元阵列（61）包括以多个行和列排列的多个三晶体管型存储单元（10）。 对应于存储单元阵列（61）的每列，提供多对写位线（WB1，WB2）和多条读位线（RB）。 对应于存储单元阵列（61）的每一行，提供多个写入字线（WWL）和多条读取字线（RWL）。 信息通过写入位线对（WB1，WB2）中的相应的一个写位线被写入奇数行的存储单元（10），并且信息通过相应的其他写入写入偶数行的存储单元（10） 写位线对（WB1，WB2）的位线。 读出放大器（30）连接到写入位线对（WB1，WB2）中的每一对。 在写入操作时，相对于非选择列中的存储单元（10），读出放大器（30）执行刷新操作。
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