Abstract:
Example embodiments relate to a non-volatile memory device and a method of forming the same. A non-volatile memory device according to example embodiments may include a conductive pattern provided on the semiconductor substrate. A tunnel insulator may be provided on the conductive pattern. A memory gate structure may be provided on the semiconductor substrate so as to cover a first end of the conductive pattern. The first end may include an upward tapering, first protrusion. A select gate structure may be provided on the semiconductor substrate so as to cover the second end of the conductive pattern. The second end may include an upward tapering, second protrusion. The coverage of the first protrusion by the memory gate structure may be greater than the coverage of the second protrusion by the select gate structure.
Abstract:
A non-volatile memory integrated circuit device and a method of fabricating the same are disclosed. The non-volatile memory integrated circuit device includes a semiconductor substrate, a tunneling dielectric layer, a memory gate and a select gate, a floating junction region, a bit line junction region and a common source region, and a tunneling-prevention dielectric layer pattern. The tunneling dielectric layer is formed on the semiconductor substrate. The memory gate and a select gate are formed on the tunneling dielectric layer to be spaced apart from each other. The floating junction region is formed within the semiconductor substrate between the memory gate and the select gate, the bit line junction region is formed opposite the floating junction region with respect to the memory gate, and a common source region is formed opposite the floating junction region with respect to the select gate. The tunneling-prevention dielectric layer pattern is interposed between the semiconductor substrate and the tunneling dielectric layer, and is configured to overlap part of the memory gate.
Abstract:
A method of manufacturing an EEPROM cell includes growing a first oxide layer on a semiconductor substrate; forming a first conductive layer on the first oxide layer; forming a first conductive pattern and a tunneling oxide layer by patterning the first conductive layer and the first oxide layer, the tunneling oxide layer being disposed under the first conductive pattern; forming a gate oxide layer on sidewalls of the first conductive pattern and the substrate and forming a second conductive pattern on both sides of the first conductive pattern; forming a conductive layer for a floating gate by electrically connecting the first conductive pattern to the second conductive pattern; forming a coupling oxide layer on the conductive layer for the floating gate; forming a third conductive layer on the coupling oxide layer; and forming a select transistor and a control transistor by patterning the third conductive layer, the coupling oxide layer, and the conductive layer for the floating gate. The select transistor is spaced apart from the control transistor. The select transistor, which is formed on the tunneling oxide layer, includes a gate stack formed of a select gate, a first coupling oxide pattern, and a first floating gate, and the control transistor includes a gate stack formed of a control gate, a second coupling oxide pattern, and a second floating gate.
Abstract:
A self-aligned 1 bit silicon oxide nitride oxide silicon (SONOS) cell and a method of fabricating the same has high uniformity between adjacent SONOS cells, since the lengths of nitride layers do not vary due to misalignment when etching word lines of the 1 bit SONOS cells. An insulating layer pattern that forms a sidewall of a word line is formed on a semiconductor substrate, and a word line for a gate is formed on the sidewall thereof. Etching an ONO layer using a self-aligned etching spacer provides uniform adjacent SONOS cells.
Abstract:
A self-aligned 1 bit silicon oxide nitride oxide silicon (SONOS) cell and a method of fabricating the same has high uniformity between adjacent SONOS cells, since the lengths of nitride layers do not vary due to misalignment when etching word lines of the 1 bit SONOS cells. An insulating layer pattern that forms a sidewall of a word line is formed on a semiconductor substrate, and a word line for a gate is formed on the sidewall thereof. Etching an ONO layer using a self-aligned etching spacer provides uniform adjacent SONOS cells.
Abstract:
A method and apparatus for using header information of stereoscopic image data is provided. The method includes using three-dimensional reproduction period information related to three-dimensionally reproduced stereoscopic image data of image data recorded in a payload region of the stereoscopic image bitstream, in a header region of the stereoscopic image bitstream; recording camera information related to cameras used for obtaining a stereoscopic image, in the header region; recording parallax information between base and additional images of the stereoscopic image in the header region; and recording the image data in the payload region of the stereoscopic image bitstream.
Abstract:
Provided is a method of receiving multiview camera parameters for a stereoscopic image. The method includes: extracting multiview camera parameter information for a predetermined data section from a received stereoscopic image data stream; extracting matrix information including at least one of translation matrix information and rotation matrix information for the predetermined data section from the multiview camera parameter information; and restoring coordinate systems of multiview cameras by using the extracted matrix information.
Abstract:
Provided are a method and apparatus for encoding and decoding a datastream into which multiview image information is inserted. The method of decoding a multiview image datastream includes extracting multiview image information including information on at least one view image of a multiview image, from at least one elementary stream of the multiview image datastream; extracting a multiview image parameter regarding the multiview image based on the number of elementary streams and a correlation between view images of the multiview image; and restoring the multiview image by using the extracted multiview image parameter and the extracted multiview image information.
Abstract:
Provided are a method and apparatus for receiving and generating an image data stream including a three dimensional (3D) image. The method of receiving an image data stream includes receiving an image data stream including at least one of two dimensional (2D) and 3D image data periods; extracting local 3D image parameters, which are parameters of each image data period, from the image data stream; and restoring at least one of 2D and 3D images by using the local 3D image parameters. In the method, each 3D image is composed of at least one of a base image and an additional image, and the local 3D image parameters include stereoscopic arrangement order information representing an arrangement order of the base image and additional image of the 3D image.
Abstract:
Provided are an apparatus and method for efficiently and dynamically allocating a bandwidth on a Time Division Multiple Access-based Passive Optical Network (TDMA PON). The dynamic bandwidth allocation apparatus for uplink data transmission of a plurality of Optical Network Units (ONUs) including a plurality of class queues corresponding to Transmission Container (T-CONT) types, the plurality of ONUs connected to an Optical Line Terminal (OLT) on a Passive Optical Network (PON), includes: a class queue information storage unit storing information regarding a bandwidth allocation period and an allocatable bandwidth amount for each T-CONT type; an allocation check table unit checking the bandwidth allocation period for the T-CONT type received from the class queue information storage unit, and determining an allocatable bandwidth amount for the T-CONT type; and a bandwidth allocation unit allocating an uplink bandwidth to the T-CONT type with reference to the bandwidth allocation period and the allocatable bandwidth amount for the T-CONT type, and re-allocating to each ONU an uplink bandwidth remaining after allocating a total uplink bandwidths to all T-CONT types.