公开(公告)号：US07872498B2

公开(公告)日：2011-01-18

申请号：US12555300

申请日：2009-09-08

申请人： Daeyun Shim ,  Min-Kyu Kim ,  Gyudong Kim ,  Keewook Jung ,  Seung Ho Hwang

发明人： Daeyun Shim ,  Min-Kyu Kim ,  Gyudong Kim ,  Keewook Jung ,  Seung Ho Hwang

IPC分类号： H03K19/0175

CPC分类号： H04L5/20

摘要： In some embodiments, a chip includes transmitters to transmit differential signals on conductors; and current mode circuitry to selectively modulate a common mode voltage of the differential signals to communicate data. In other embodiments, a system includes a first chip to transmit first and second differential signals on conductors, and a second chip. The second chip includes receivers to receive the first and second differential signals from the conductors and provide received signals representative thereof, and current mode circuitry to selectively modulate a common mode voltage of either the first or second differential signals to communicate data and wherein the first chip includes common mode detection circuitry to detect changes in the common mode voltage. Other embodiments are described and claimed.

摘要翻译： 在一些实施例中，芯片包括在导体上传输差分信号的发射器; 以及电流模式电路，用于选择性地调制差分信号的共模电压以传送数据。 在其他实施例中，系统包括用于在导体上传输第一和第二差分信号的第一芯片和第二芯片。 第二芯片包括接收器，用于从导体接收第一和第二差分信号并提供表示其的接收信号;以及电流模式电路，用于选择性地调制第一或第二差分信号的共模电压以传送数据，并且其中第一芯片 包括用于检测共模电压变化的共模检测电路。 描述和要求保护其他实施例。

公开(公告)号：US07847583B2

公开(公告)日：2010-12-07

申请号：US12275686

申请日：2008-11-21

申请人： Gyudong Kim ,  Min-Kyu Kim

发明人： Gyudong Kim ,  Min-Kyu Kim

IPC分类号： H03K17/16

CPC分类号： H04L25/0292 ,  H03F3/45179 ,  H03F3/45632 ,  H03K5/2481 ,  H04L5/18 ,  H04L25/0272

摘要： An output amplifier is provided for use in a bidirectional communications interface, for example, connecting a transmitter and a receiver to a transmission line. The output amplifier includes a differential amplifier pair connected to output circuitry. The differential amplifier pair receives differential data signal pairs from each of a transmission line and a transmitter. The output circuitry receives signals from the differential amplifier pair and, in response, forms single-ended output logic signals. The output amplifier suppresses electronic input noise throughput using an asymmetric transfer characteristic that offsets output signal logic levels with respect to input noise signal levels. The asymmetric transfer characteristic is produced by skewing a transfer characteristic of the differential amplifier pair using an asymmetrical transistor configuration at an output side of the differential amplifier pair. The output logic signals represent data received on the transmission line, and are provided to the receiver.

摘要翻译： 输出放大器被提供用于双向通信接口，例如将发射器和接收器连接到传输线。 输出放大器包括连接到输出电路的差分放大器对。 差分放大器对从传输线和发送器中的每一个接收差分数据信号对。 输出电路从差分放大器对接收信号，作为响应，形成单端输出逻辑信号。 输出放大器使用偏移相对于输入噪声信号电平的输出信号逻辑电平的非对称传输特性来抑制电子输入噪声吞吐量。 非对称传输特性是通过在差分放大器对的输出侧使用不对称晶体管配置来歪斜差分放大器对的传输特性而产生的。 输出逻辑信号表示在传输线上接收的数据，并提供给接收机。

公开(公告)号：US20100142419A1

公开(公告)日：2010-06-10

申请号：US12573847

申请日：2009-10-05

申请人： Gyudong Kim ,  Min-Kyu Kim

发明人： Gyudong Kim ,  Min-Kyu Kim

IPC分类号： H04B3/30

CPC分类号： H04B3/30 ,  H04L25/0276 ,  H04L25/085

摘要： A bidirectional communications interface is provided that connects a transmitter and a receiver, or a transceiver, to a transmission line. Under an embodiment, the bidirectional interface generates positive and negative polarity data signals using two separate differential amplifiers that receive differential signal pairs from each side of a differential link to the transmission line and the transmitter. The bidirectional interface controls common mode rejection in each of the separate differential amplifiers using bias signals generated in response to an output common mode feedback voltage from each of the differential amplifiers. An output amplifier combines the positive and negative polarity data signals to form single-ended output logic signals. The output logic signals represent data received on the transmission line, and are provided to the receiver.

摘要翻译： 提供了将发射器和接收器或收发器连接到传输线的双向通信接口。 在一个实施例中，双向接口使用两个单独的差分放大器产生正极性和负极性数据信号，差分放大器从差分链路的每一侧接收到传输线和发射器的差分信号对。 双向接口通过响应于来自每个差分放大器的输出共模反馈电压产生的偏置信号来控制每个单独的差分放大器中的共模抑制。 输出放大器组合正极性和负极性数据信号，形成单端输出逻辑信号。 输出逻辑信号表示在传输线上接收的数据，并提供给接收机。

公开(公告)号：US20090137208A1

公开(公告)日：2009-05-28

申请号：US12275686

申请日：2008-11-21

申请人： Gyudong Kim ,  Min-Kyu Kim

发明人： Gyudong Kim ,  Min-Kyu Kim

IPC分类号： H04B15/00 ,  H03K17/16 ,  H04B1/04 ,  H04B1/10

CPC分类号： H04L25/0292 ,  H03F3/45179 ,  H03F3/45632 ,  H03K5/2481 ,  H04L5/18 ,  H04L25/0272

摘要： An output amplifier is provided for use in a bidirectional communications interface, for example, connecting a transmitter and a receiver to a transmission line. The output amplifier includes a differential amplifier pair connected to output circuitry. The differential amplifier pair receives differential data signal pairs from each of a transmission line and a transmitter. The output circuitry receives signals from the differential amplifier pair and, in response, forms single-ended output logic signals. The output amplifier suppresses electronic input noise throughput using an asymmetric transfer characteristic that offsets output signal logic levels with respect to input noise signal levels. The asymmetric transfer characteristic is produced by skewing a transfer characteristic of the differential amplifier pair using an asymmetrical transistor configuration at an output side of the differential amplifier pair. The output logic signals represent data received on the transmission line, and are provided to the receiver.

摘要翻译： 输出放大器被提供用于双向通信接口，例如将发射器和接收器连接到传输线。 输出放大器包括连接到输出电路的差分放大器对。 差分放大器对从传输线和发送器中的每一个接收差分数据信号对。 输出电路从差分放大器对接收信号，作为响应，形成单端输出逻辑信号。 输出放大器使用偏移相对于输入噪声信号电平的输出信号逻辑电平的非对称传输特性来抑制电子输入噪声吞吐量。 非对称传输特性是通过在差分放大器对的输出侧使用不对称晶体管配置来歪斜差分放大器对的传输特性而产生的。 输出逻辑信号表示在传输线上接收的数据，并提供给接收机。

公开(公告)号：US07269673B2

公开(公告)日：2007-09-11

申请号：US10781405

申请日：2004-02-18

申请人： Ook Kim ,  Eric Lee ,  Gyudong Kim ,  Zeehoon Jang ,  Baegin Sung ,  Nam Hoon Kim ,  Gijung Ahn ,  Seung Ho Hwang

发明人： Ook Kim ,  Eric Lee ,  Gyudong Kim ,  Zeehoon Jang ,  Baegin Sung ,  Nam Hoon Kim ,  Gijung Ahn ,  Seung Ho Hwang

IPC分类号： G06F13/38

CPC分类号： G06F13/385

摘要： A cable including circuitry for asserting information to a user or external device and a system including such a cable. The cable can include conductors, a memory storing cable data, and circuitry configured to respond to a request received on at least one of the conductors by accessing at least some of the cable data and asserting the accessed data serially to at least one of the conductors (e.g., for transmission to an external device). Other aspects of the invention are methods for accessing cable data stored in a cable and optionally using the data (e.g., to implement equalization). The cable data can be indicative of all or some of cable type, grade, speed, length, and impedance, a date code, a frequency-dependent attenuation table, far-end crosstalk and EMI-related coefficients, common mode radiation, intra pair skew, and other information. The cable can include a radiation-emitting element and circuitry for generating driving signals for causing the radiation-emitting element to produce an appropriate color, brightness, and/or blinking pattern.

摘要翻译： 包括用于向用户或外部设备断言信息的电路的电缆以及包括这种电缆的系统。 电缆可以包括导体，存储电缆数据的存储器和经配置以通过访问至少一些电缆数据来响应于在至少一个导体上接收到的请求的电路，并且将所访问的数据串行地认定到至少一个导体 （例如，用于传输到外部设备）。 本发明的其他方面是用于访问存储在电缆中并且可选地使用数据（例如，实现均衡）的电缆数据的方法。 电缆数据可以表示电缆类型，等级，速度，长度和阻抗的全部或一些，日期代码，频率相关衰减表，远端串扰和EMI相关系数，共模辐射，内部对 歪斜等信息。 电缆可以包括辐射发射元件和用于产生用于使辐射发射元件产生适当的颜色，亮度和/或闪烁图案的驱动信号的电路。

公开(公告)号：US20060256744A1

公开(公告)日：2006-11-16

申请号：US11441669

申请日：2006-05-25

申请人： Gyudong Kim ,  Min-Kyu Kim

发明人： Gyudong Kim ,  Min-Kyu Kim

IPC分类号： H04B1/58 ,  H04B3/30

CPC分类号： H04B3/30 ,  H04L25/0276 ,  H04L25/085

摘要： A bidirectional communications interface is provided that connects a transmitter and a receiver, or a transceiver, to a transmission line. Under an embodiment, the bidirectional interface generates positive and negative polarity data signals using two separate differential amplifiers that receive differential signal pairs from each side of a differential link to the transmission line and the transmitter. The bidirectional interface controls common mode rejection in each of the separate differential amplifiers using bias signals generated in response to an output common mode feedback voltage from each of the differential amplifiers. An output amplifier combines the positive and negative polarity data signals to form single-ended output logic signals. The output logic signals represent data received on the transmission line, and are provided to the receiver.

公开(公告)号：US20060055822A1

公开(公告)日：2006-03-16

申请号：US11219323

申请日：2005-09-01

申请人： Stephen Keating ,  Russel Martin ,  Victor Da Costa ,  Gyudong Kim

发明人： Stephen Keating ,  Russel Martin ,  Victor Da Costa ,  Gyudong Kim

IPC分类号： H04N11/00

CPC分类号： H04L7/02 ,  H04N5/208 ,  H04N5/21

摘要： A jitter correction apparatus and method are disclosed. In one embodiment, the apparatus has a rising edge corrector to receive a jittered signal and to output a jitter corrected rising edge of the jittered signal. The apparatus may also have a falling edge corrector to receive the jittered signal and to output a jitter corrected falling edge of the jittered signal. The jitter correction apparatus may include an output device to receive the jitter corrected rising edge, to receive the jitter corrected falling edge, and to output a jitter corrected signal.

公开(公告)号：US20050195894A1

公开(公告)日：2005-09-08

申请号：US10794015

申请日：2004-03-05

申请人： Ook Kim ,  Gyudong Kim

发明人： Ook Kim ,  Gyudong Kim

IPC分类号： H03D1/04 ,  H03K5/01

CPC分类号： H04L25/03019

摘要： In preferred embodiments, an adaptive equalization circuit including at least two equalization filters (each for equalizing a signal transmitted over a multi-channel serial link) and control circuitry for generating an equalization control signal for use by all the filters. The control circuitry generates the control signal in response to an equalized signal produced by one of the filters, and asserts the control signal to all the filters. Preferably, one filter generates an equalized fixed pattern signal in response to a fixed pattern signal (e.g., a clock signal), each other filter equalizes a data signal, and the control circuitry generates the control signal in response to the equalized fixed pattern signal. In other embodiments, the invention is an adaptive equalization circuit including an equalization filter and circuitry for generating a control signal for the filter in response to a signal indicative of a predetermined fixed pattern, a receiver including an adaptive equalization circuit, a system including such a receiver, and a method for adaptive equalization of signals received over a multi-channel serial link.

摘要翻译： 在优选实施例中，自适应均衡电路包括至少两个均衡滤波器（每个用于均衡通过多通道串行链路传输的信号）和用于产生用于所有滤波器的均衡控制信号的控制电路。 控制电路响应于由滤波器之一产生的均衡信号而产生控制信号，并将控制信号置为全部滤波器。 优选地，一个滤波器响应于固定模式信号（例如，时钟信号）产生均衡的固定模式信号，每个其他滤波器均衡数据信号，并且控制电路响应于均衡的固定模式信号而产生控制信号。 在其他实施例中，本发明是一种自适应均衡电路，包括均衡滤波器和用于响应于指示预定固定模式的信号产生用于滤波器的控制信号的电路，包括自适应均衡电路的接收机， 接收机和用于通过多声道串行链路接收的信号的自适应均衡的方法。

公开(公告)号：US06809567B1

公开(公告)日：2004-10-26

申请号：US09989645

申请日：2001-11-20

申请人： Ook Kim ,  Hung Sung Li ,  Inyeol Lee ,  Gyudong Kim ,  Yongman Lee

发明人： Ook Kim ,  Hung Sung Li ,  Inyeol Lee ,  Gyudong Kim ,  Yongman Lee

IPC分类号： H03L700

CPC分类号： H03K23/542 ,  G06F1/06 ,  H03K5/15013 ,  H03L7/0891 ,  H03L7/0995

摘要： A system and method for multiple-phase clock generation is disclosed. In one embodiment, a multiple-stage voltage controlled oscillator (“VCO”) transmits a plurality of clock phases to a clock divider circuit which produces the desired number of clock phase outputs. The clock divider circuit in this embodiment includes a state machine, e.g., a modified Johnson counter, that provides a plurality of divided down clock phases, each of which is connected to a separate modified shift register. Each modified shift register contains D-type flip-flops and each D-type flip-flop provides a separate clock phase output. In one embodiment the number of clock phase outputs of the multiple-phase clock is a function of the number of VCO clock phases times the number of desired states in the modified Johnson counter.

摘要翻译： 公开了一种用于多相时钟产生的系统和方法。 在一个实施例中，多级压控振荡器（“VCO”）将多个时钟相位发送到产生期望数量的时钟相位输出的时钟分频器电路。 该实施例中的时钟分频器电路包括一个状态机，例如修改的约翰逊计数器，其提供多个划分的下降时钟相位，每个分频下降沿连接到单独的修改的移位寄存器。 每个修改的移位寄存器包含D型触发器，每个D型触发器提供单独的时钟相位输出。 在一个实施例中，多相时钟的时钟相位输出的数量是VCO时钟相位数乘以修改的约翰逊计数器中期望状态数量的函数。

公开(公告)号：US06717478B1

公开(公告)日：2004-04-06

申请号：US09989587

申请日：2001-11-20

申请人： Ook Kim ,  Hung Sung Li ,  Inyeol Lee ,  Gyudong Kim ,  Yongman Lee

发明人： Ook Kim ,  Hung Sung Li ,  Inyeol Lee ,  Gyudong Kim ,  Yongman Lee

IPC分类号： H03B2700

CPC分类号： H03L7/0995 ,  H03B5/24 ,  H03B27/00 ,  H03L7/0891

摘要： A voltage controlled oscillator (“VCO”) circuit capable of generating signals with reduced jitter and/or low-phase noise is provided. One embodiment provides a plurality of cascaded VCO cells, where each VCO cell can include a source coupled differential pair, a bias transistor connected to the differential pair for biasing the differential pair, a resistive load pair connected to the differential pair, and a voltage controlled capacitor pair or varactor pair connected to the differential pair. The varactors provide control over the frequency of the oscillations produced by the VCO circuit in combination with a control voltage. A phase frequency detector combined with a charge pump and loop filter provide the control voltage.

摘要翻译： 提供了能够产生具有降低的抖动和/或低相位噪声的信号的压控振荡器（“VCO”）电路。 一个实施例提供多个级联VCO单元，其中每个VCO单元可以包括源极耦合差分对，连接到差分对的偏置晶体管，用于偏置差分对，连接到差分对的电阻负载对，以及电压控制 电容器对或变容二极管对连接到差分对。 变容二极管提供对由VCO电路产生的振荡频率与控制电压的组合的控制。 与电荷泵和环路滤波器组合的相位检波器提供控制电压。