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    ONE TRANSISTOR AND ONE FERROELECTRIC CAPACITOR MEMORY CELLS IN DIAGONAL ARRANGEMENTS
    42.
    发明申请
    ONE TRANSISTOR AND ONE FERROELECTRIC CAPACITOR MEMORY CELLS IN DIAGONAL ARRANGEMENTS 审中-公开

    公开(公告)号：US20200091162A1

    公开(公告)日：2020-03-19

    申请号：US16132281

    申请日：2018-09-14

    Applicant: Intel Corporation

    Inventor： Daniel H. Morris ,  Uygar E. Avci ,  Ian A. Young

    IPC: H01L27/11507 ,  H01L27/108 ,  H01L23/522 ,  H01L23/532 ,  G11C11/22

    Abstract: Described herein are one access transistor and one ferroelectric capacitor (1T-1FE-CAP) memory cells in diagonal arrangements, as well as corresponding methods and devices. When access transistors of memory cells are implemented as FinFETs, then, in a first diagonal arrangement, memory cells are arranged so that the BLs for the cells are diagonal with respect to the fins of the access transistors of the cells, while the WLs for the cells are perpendicular to the fins. In a second diagonal arrangement, memory cells are arranged so that the fins of the access transistors of the cells are diagonal with respect to the WLs for the cells, while the BLs for the cells are perpendicular to the WLs. Such diagonal arrangements may advantageously allow achieving high layout densities of 1T-1FE-CAP memory cells and may benefit from the re-use of front-end transistor process technology with relatively minor adaptations.

    Polarization gate stack SRAM
    43.
    发明授权
    Polarization gate stack SRAM 有权

    公开(公告)号：US10559349B2

    公开(公告)日：2020-02-11

    申请号：US16078582

    申请日：2016-04-01

    Applicant: Intel Corporation

    Inventor： Daniel H. Morris ,  Uygar E. Avci ,  Ian A. Young

    IPC: G11C11/00 ,  G11C11/412 ,  G11C8/16 ,  G11C11/419 ,  H01L27/11 ,  G11C11/22

    Abstract: One embodiment provides an apparatus. The apparatus includes a first inverter comprising a first pull up transistor and a first pull down transistor; a second inverter cross coupled to the first inverter, the second inverter comprising a second pull up transistor and a second pull down transistor; a first access transistor coupled to the first inverter; and a second access transistor coupled to the second inverter. A gate electrode of one transistor of each inverter comprises a polarization layer.

    SAVE-RESTORE CIRCUITRY WITH METAL-FERROELECTRIC-METAL DEVICES
    44.
    发明申请
    SAVE-RESTORE CIRCUITRY WITH METAL-FERROELECTRIC-METAL DEVICES 审中-公开

    公开(公告)号：US20190043549A1

    公开(公告)日：2019-02-07

    申请号：US16144896

    申请日：2018-09-27

    Applicant: Intel Corporation

    Inventor： Kaushik Vaidyanathan ,  Daniel H. Morris ,  Huichu Liu ,  Dileep J. Kurian ,  Uygar E. Avci ,  Tanay Karnik ,  Ian A. Young

    IPC: G11C11/22 ,  G11C11/413 ,  G06F1/32

    Abstract: Embodiments include apparatuses, methods, and systems associated with save-restore circuitry including metal-ferroelectric-metal (MFM) devices. The save-restore circuitry may be coupled to a bit node and/or bit bar node of a pair of cross-coupled inverters to save the state of the bit node and/or bit bar node when an associated circuit block transitions to a sleep state, and restore the state of the bit node and/or bit bar node when the associated circuit block transitions from the sleep state to an active state. The save-restore circuitry may be used in a flip-flop circuit, a register file circuit, and/or another suitable type of circuit. The save-restore circuitry may include a transmission gate coupled between the bit node (or bit bar node) and an internal node, and an MFM device coupled between the internal node and a plate line. Other embodiments may be described and claimed.

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