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    Latch clustering with proximity to local clock buffers
    41.
    发明授权
    Latch clustering with proximity to local clock buffers 失效
    锁定聚类，靠近本地时钟缓冲区

    公开(公告)号：US08677299B1

    公开(公告)日：2014-03-18

    申请号：US13736648

    申请日：2013-01-08

    Applicant: International Business Machines Corporation

    Inventor： Charles Jay Alpert ,  Zhuo Li ,  Gi-Joon Nam ,  David Anthony Papa ,  Chin Ngai Sze ,  Natarajan Viswanathan

    IPC: G06F17/50

    CPC classification number: G06F17/5054 ,  G06F2217/62

    Abstract: A method, system, and computer usable program product for latch clustering with proximity to local clock buffers (LCBs) where an algorithm is used to cluster a plurality of latches into a first plurality of groups in an integrated circuit. A number of groups in the first plurality of groups of clustered latches is determined. A plurality of LCBs are added where a number of added LCBs is the same as the number of groups in the first plurality of groups. A cluster radius for a subset of the first plurality of groups of clustered latches is determined, a group in the subset having a cluster radius that is a maximum cluster radius in the subset. The plurality of latches are reclustered into a second plurality of groups responsive to the maximum cluster radius exceeding a radius threshold, the second plurality of groups exceeding the first plurality of groups by one.

    Abstract translation: 一种用于与本地时钟缓冲器（LCB）接近的锁存器聚类的方法，系统和计算机可用程序产品，其中使用算法将多个锁存器聚集成集成电路中的第一组多个组。 确定第一组多个群集锁存器中的多个组。 添加多个LCB，其中添加的LCB的数量与第一组中的组的数量相同。 确定第一组多个聚集锁存器的子集的簇半径，该子集中的组具有作为该子集中的最大簇半径的簇半径。 响应于最大簇半径超过半径阈值，将多个锁存器重新聚集成第二组，第二组群超过第一组多组。

    MULTI-STAGE ELECTRONIC DESIGN AUTOMATION PARAMETER TUNING
    43.
    发明公开
    MULTI-STAGE ELECTRONIC DESIGN AUTOMATION PARAMETER TUNING 审中-公开

    公开(公告)号：US20230195993A1

    公开(公告)日：2023-06-22

    申请号：US17645093

    申请日：2021-12-20

    Applicant: International Business Machines Corporation

    Inventor： Gi-Joon Nam ,  Jinwook Jung ,  Alexey Y. Lvov ,  Lakshmi N. Reddy ,  Hua Xiang ,  Rongjian Liang

    IPC: G06F30/398

    CPC classification number: G06F30/398

    Abstract: Techniques regarding parameter tuning for an EDA protocol are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise a tuning component that tunes an electronic design automation protocol via a cooperative co-evolutionary optimization framework that shares parameter knowledge across multiple stages of the electronic design automation protocol.

    AUTONOMOUS PLACEMENT TO SATISFY SELF-ALIGNED DOUBLE PATTERNING CONSTRAINTS
    44.
    发明申请
    AUTONOMOUS PLACEMENT TO SATISFY SELF-ALIGNED DOUBLE PATTERNING CONSTRAINTS 审中-公开

    公开(公告)号：US20200057836A1

    公开(公告)日：2020-02-20

    申请号：US16103011

    申请日：2018-08-14

    Applicant: International Business Machines Corporation

    Inventor： Hua Xiang ,  Gustavo Enrique Tellez ,  Shyam Ramji ,  Gi-Joon Nam

    IPC: G06F17/50

    Abstract: Techniques regarding functional placement of one or more logic gates in a periodic circuit row configuration are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise an optimization component, operatively coupled to the processor, that can determine functional placement of a logic gate in a self-aligned double patterning process that can form a periodic circuit row configuration.

    INTEGRATED CIRCUIT BUFFERING SOLUTIONS CONSIDERING SINK DELAYS
    45.
    发明申请
    INTEGRATED CIRCUIT BUFFERING SOLUTIONS CONSIDERING SINK DELAYS 审中-公开

    公开(公告)号：US20190278873A1

    公开(公告)日：2019-09-12

    申请号：US16423242

    申请日：2019-05-28

    Applicant: International Business Machines Corporation

    Inventor： Ying Zhou ,  Stephen T. Quay ,  Lakshmi N. Reddy ,  Gustavo E. Tellez ,  Gi-Joon Nam ,  Jiang Hu

    IPC: G06F17/50

    Abstract: Optimizing timing in a VLSI circuit by generating a set of buffer solutions and determining a most critical delay and a sum of critical delays for each solution in the set of solutions. Quantifying a relationship between the most critical delay and the sum of critical delays for each solution. Comparing each solution's quantified relationship to the quantified relationship of each other solution in the set of solutions. Identifying, based on the comparing of each solution's relationship to the relationship of each other solution in the set of solutions, at least one solution in the set of solutions to have a worse relationship between the most critical delay and the sum of critical delays than the other solutions in the set of solutions. Pruning the at least one solution from the set of solutions.

    Integrated circuit buffering solutions considering sink delays
    46.
    发明授权
    Integrated circuit buffering solutions considering sink delays 有权

    公开(公告)号：US10372837B2

    公开(公告)日：2019-08-06

    申请号：US15896176

    申请日：2018-02-14

    Applicant: International Business Machines Corporation

    Inventor： Ying Zhou ,  Stephen T. Quay ,  Lakshmi N. Reddy ,  Gustavo E. Tellez ,  Gi-Joon Nam ,  Jiang Hu

    IPC: G06F17/50

    Abstract: Optimizing timing in a VLSI circuit by generating a set of buffer solutions and determining a most critical delay and a sum of critical delays for each solution in the set of solutions. Quantifying a relationship between the most critical delay and the sum of critical delays for each solution. Comparing each solution's quantified relationship to the quantified relationship of each other solution in the set of solutions. Identifying, based on the comparing of each solution's relationship to the relationship of each other solution in the set of solutions, at least one solution in the set of solutions to have a worse relationship between the most critical delay and the sum of critical delays than the other solutions in the set of solutions. Pruning the at least one solution from the set of solutions.

    Triple and quad coloring shape layouts
    48.
    发明授权
    Triple and quad coloring shape layouts 有权

    公开(公告)号：US10223496B2

    公开(公告)日：2019-03-05

    申请号：US15466525

    申请日：2017-03-22

    Applicant: International Business Machines Corporation

    Inventor： Alexey Y. Lvov ,  Gi-Joon Nam ,  Gustavo Enrique Tellez

    IPC: G06F17/50

    Abstract: Techniques related to triple and quad coloring of shape layouts are provided. A computer-implemented method comprises coloring, by a system operatively coupled to a processor, a shape layout with a plurality of colors in accordance with a defined design rule based on a determination that a first defined shape within the shape layout satisfies a layout specification and a second defined shape within the shape layout satisfies a defined rule.

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