公开(公告)号：US20240104282A1

公开(公告)日：2024-03-28

申请号：US17934216

申请日：2022-09-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Benjamin Neil Trombley ,  Chung-Lung K. Shum ,  Paul G. Villarrubia ,  K. Paul Muller ,  Michael Hemsley Wood ,  Daniel Arthur Gay ,  Hua Xiang ,  Karl Evan Smock Anderson ,  Erica Stuecheli ,  Michael Alexander Bowen ,  Randall J. Darden

IPC: G06F30/392 ,  G06F30/398

CPC classification number: G06F30/392 ,  G06F30/398

Abstract: A method, system, and computer program product for bit flip aware latch placement in integrated circuit generation are provided. The method identifies a chip design for an integrated circuit. A set of chip design constraints, associated with the chip design, is identified. A set of checking groups, associated with a plurality of latches to be placed in the chip design, is determined. Based on the set of chip design constraints and the set of checking groups, a placement scheme for the plurality of latches is selected. The method places the plurality of latches within the chip design based on the placement scheme and the set of checking groups.

公开(公告)号：US11120192B1

公开(公告)日：2021-09-14

申请号：US16853180

申请日：2020-04-20

Applicant: International Business Machines Corporation

Inventor： Hua Xiang ,  Gustavo E. Tellez ,  Gi-Joon Nam ,  Jennifer Kazda

IPC: G06F30/394 ,  G06F30/392 ,  G06F119/12

Abstract: A method for enhancing routability in a cell-based design includes: obtaining a layout corresponding to a placement of cells in the cell-based design; identifying one or more areas of the layout where routability is predicted to be constrained; selectively adding white spaces to the identified one or more areas of the layout where routability is predicted to be constrained to thereby generate a modified layout; legalizing placement of the modified layout; and running a detailed routing on the modified layout.

公开(公告)号：US12277375B2

公开(公告)日：2025-04-15

申请号：US17649180

申请日：2022-01-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hua Xiang ,  Benjamin Neil Trombley ,  Gi-Joon Nam ,  Gustavo E. Tellez ,  Paul G. Villarrubia

IPC: G06F30/392

Abstract: Embodiments are provided for providing power staple avoidance during routing in a computing system by a processor. One or more transistor gates may be shifted in each row of an integrated circuit to avoid alignment of cell pins and power staples for executing a routing operation, where the circuit row is partitioned into segments based on one or more fixed objects.

公开(公告)号：US20230195993A1

公开(公告)日：2023-06-22

申请号：US17645093

申请日：2021-12-20

Applicant: International Business Machines Corporation

Inventor： Gi-Joon Nam ,  Jinwook Jung ,  Alexey Y. Lvov ,  Lakshmi N. Reddy ,  Hua Xiang ,  Rongjian Liang

IPC: G06F30/398

CPC classification number: G06F30/398

Abstract: Techniques regarding parameter tuning for an EDA protocol are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise a tuning component that tunes an electronic design automation protocol via a cooperative co-evolutionary optimization framework that shares parameter knowledge across multiple stages of the electronic design automation protocol.

公开(公告)号：US20200057836A1

公开(公告)日：2020-02-20

申请号：US16103011

申请日：2018-08-14

Applicant: International Business Machines Corporation

Inventor： Hua Xiang ,  Gustavo Enrique Tellez ,  Shyam Ramji ,  Gi-Joon Nam

IPC: G06F17/50

Abstract: Techniques regarding functional placement of one or more logic gates in a periodic circuit row configuration are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise an optimization component, operatively coupled to the processor, that can determine functional placement of a logic gate in a self-aligned double patterning process that can form a periodic circuit row configuration.

公开(公告)号：US12124789B2

公开(公告)日：2024-10-22

申请号：US17645093

申请日：2021-12-20

Applicant: International Business Machines Corporation

Inventor： Gi-Joon Nam ,  Jinwook Jung ,  Alexey Y. Lvov ,  Lakshmi N. Reddy ,  Hua Xiang ,  Rongjian Liang

IPC: G06F30/398

CPC classification number: G06F30/398

Abstract: Techniques regarding parameter tuning for an EDA protocol are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise a tuning component that tunes an electronic design automation protocol via a cooperative co-evolutionary optimization framework that shares parameter knowledge across multiple stages of the electronic design automation protocol.

公开(公告)号：US11087062B1

公开(公告)日：2021-08-10

申请号：US16936146

申请日：2020-07-22

Applicant: International Business Machines Corporation

Inventor： Hua Xiang ,  Gi-Joon Nam ,  Gustavo Enrique Tellez

IPC: G06F30/392 ,  G06F30/398 ,  G06F30/373 ,  G06F30/394

Abstract: Techniques for dynamically generating self-aligned double patterning (SADP) gate regions based on gate distribution and the relocation of the gates to their matched region are provided. In one aspect, a method for generating SADP gate regions in a circuit design includes: obtaining a circuit design having SADP gates, and a placement solution for the SADP gates that, while non-overlapping, violates SADP track routing matching requirements; determining approximate locations of SADP regions in the circuit design; assigning the SADP gates to the SADP regions using a minimum-cost maximum-flow (min-cost max-flow) process; and identifying, once all of the SADP gates have been assigned to the SADP regions, non-overlapping locations for the SADP gates in the SADP regions.

公开(公告)号：US10796064B2

公开(公告)日：2020-10-06

申请号：US16103011

申请日：2018-08-14

Applicant: International Business Machines Corporation

Inventor： Hua Xiang ,  Gustavo Enrique Tellez ,  Shyam Ramji ,  Gi-Joon Nam

IPC: G06F17/50 ,  G06F30/398 ,  G06F30/392

Abstract: Techniques regarding functional placement of one or more logic gates in a periodic circuit row configuration are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise an optimization component, operatively coupled to the processor, that can determine functional placement of a logic gate in a self-aligned double patterning process that can form a periodic circuit row configuration.