公开(公告)号：US11621189B2

公开(公告)日：2023-04-04

申请号：US17377541

申请日：2021-07-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Nicholas Anthony Lanzillo ,  Hosadurga Shobha ,  Junli Wang ,  Lawrence A. Clevenger ,  Christopher J. Penny ,  Robert Robison ,  Huai Huang

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: A method for fabricating a semiconductor device includes forming one or more layers including at least one of a liner and a barrier along surfaces of a first interlevel dielectric (ILD) layer within a trench, after forming the one or more liners, performing a via etch to form a via opening exposing a first conductive line corresponding to a first metallization level, and forming, within the via opening and on the first conductive line, a barrier-less prefilled via including first conductive material.

公开(公告)号：US20220359394A1

公开(公告)日：2022-11-10

申请号：US17873888

申请日：2022-07-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Brent Alan Anderson ,  Lawrence A. Clevenger ,  Christopher J. Penny ,  Kisik Choi ,  Nicholas Anthony Lanzillo ,  Robert Robison

IPC: H01L23/528 ,  H01L21/768

Abstract: Integrated chips include first lines, formed on an underlying substrate. Spacers are formed conformally on sidewalls of the plurality of lines. Etch stop remnants are positioned on the sidewalls of the plurality of lines, between the spacers and the underlying substrate. Second lines are formed on the underlying substrate, between respective pairs of adjacent first lines.

公开(公告)号：US11437317B2

公开(公告)日：2022-09-06

申请号：US16786393

申请日：2020-02-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Brent Alan Anderson ,  Lawrence A. Clevenger ,  Christopher J. Penny ,  Kisik Choi ,  Nicholas Anthony Lanzillo ,  Robert Robison

IPC: H01L23/528 ,  H01L21/768

Abstract: Integrated chips and methods of forming lines in the same include forming first lines on a underlying substrate. Conformal dielectric spacers are formed on sidewalls of the first lines. Second lines are formed on the underlying substrate, in open areas between the dielectric spacers.

公开(公告)号：US20220223473A1

公开(公告)日：2022-07-14

申请号：US17683579

申请日：2022-03-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Brent Anderson ,  Lawrence A. Clevenger ,  Kisik Choi ,  Nicholas Anthony Lanzillo ,  Christopher J. Penny ,  Robert Robison

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/04 ,  H01L21/3105

Abstract: A method for fabricating a semiconductor device including a self-aligned top via includes subtractively etching a conductive layer to form at least a first conductive line on a substrate. After the subtractive etching, the method further includes forming a barrier layer along the substate and along the first conductive line, planarizing at least portions of the barrier layer to obtain at least an exposed first conductive line, recessing at least the exposed first conductive line to form a first recessed conductive line, and forming conductive material in a via opening on the first recessed conductive line.

公开(公告)号：US20220005731A1

公开(公告)日：2022-01-06

申请号：US17479045

申请日：2021-09-20

Applicant: International Business Machines Corporation

Inventor： Christopher J. Penny ,  Brent Anderson ,  Lawrence A. Clevenger ,  Robert Robison ,  Kisik Choi ,  Nicholas Anthony Lanzillo

IPC: H01L21/768 ,  H01L23/522

Abstract: A method of forming an interconnect structure includes forming at least one second-level interconnect in a sacrificial dielectric layer that is formed on an upper surface of a sacrificial etch stop layer, and removing the sacrificial dielectric layer and the sacrificial etch stop layer while maintaining the at least one second-level interconnect so as to expose an underlying dielectric layer. The method further includes depositing a replacement dielectric layer on an upper surface of the underlying dielectric layer to embed the at least one second-level interconnect in the replacement dielectric layer. Accordingly, an interconnect structure can be formed that includes one or more first-level interconnect in a dielectric layer and one or more second-level interconnects in a replacement dielectric layer stacked on the dielectric layer. The replacement dielectric layer directly contacts the dielectric layer.

公开(公告)号：US20210384123A1

公开(公告)日：2021-12-09

申请号：US16891143

申请日：2020-06-03

Applicant: International Business Machines Corporation

Inventor： Brent Anderson ,  Lawrence A. Clevenger ,  Nicholas Anthony Lanzillo ,  Christopher J. Penny ,  Kisik Choi ,  Robert Robison

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768

Abstract: Embodiments of the invention include a method of forming a multi-layer integrated circuit (IC) structure that includes forming a first dielectric layer. A first interconnect is formed in the first dielectric layer and includes a first top surface, a first bottom surface, and a first sidewall extending from an edge of the first top surface to an edge of the first bottom surface. A second interconnect is formed in the first dielectric layer and includes a second top surface, a second bottom surface, and a second sidewall extending from an edge of the second top surface to an edge of the second bottom surface. A spacing from the edge of the first top surface to the edge of the second top surface is greater than a spacing from the edge of the first bottom surface to the edge of the second bottom surface.

公开(公告)号：US11189568B2

公开(公告)日：2021-11-30

申请号：US16861267

申请日：2020-04-29

Applicant: International Business Machines Corporation

Inventor： Brent Anderson ,  Lawrence A. Clevenger ,  Nicholas Anthony Lanzillo ,  Christopher J. Penny ,  Kisik Choi ,  Robert Robison

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768

Abstract: A technique relates to an integrated circuit (IC). The IC includes a conductive line formed on a conductive via, the conductive line being formed though a dielectric material. The IC includes an etch stop layer having one or more extended portions intervening between one or more edge portions of the conductive line and the conductive via, the one or more edge portions being at a periphery of the conductive line and the conductive via, the etch stop layer including a higher dielectric breakdown than the dielectric material. The one or more extended portions of the etch stop layer cause the conductive line to be formed with a bottom part having a reduced dimension than an upper part of the conductive line.

公开(公告)号：US11171084B2

公开(公告)日：2021-11-09

申请号：US16840727

申请日：2020-04-06

Applicant: International Business Machines Corporation

Inventor： Brent Anderson ,  Lawrence A. Clevenger ,  Christopher J. Penny ,  Nicholas Anthony Lanzillo ,  Kisik Choi ,  Robert Robison

IPC: H01L23/522 ,  H01L21/768

Abstract: Embodiments of the present invention are directed to fabrication methods and resulting interconnect structures having a conductive thin metal layer on a top via that promotes the selective growth of the next level interconnect lines (the line above). In a non-limiting embodiment of the invention, a first conductive line is formed in a dielectric layer. A via is formed on the first conductive line and a seed layer is formed on the via and the dielectric layer. A surface of the seed layer is exposed and a second conductive line is deposited onto the exposed surface of the seed layer. In a non-limiting embodiment of the invention, the second conductive line is selectively grown from the seed layer.

公开(公告)号：US20210343589A1

公开(公告)日：2021-11-04

申请号：US17377541

申请日：2021-07-16

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Nicholas Anthony Lanzillo ,  Hosadurga Shobha ,  Junli Wang ,  Lawrence A. Clevenger ,  Christopher J. Penny ,  Robert Robison ,  Huai Huang

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: A method for fabricating a semiconductor device includes forming one or more layers including at least one of a liner and a barrier along surfaces of a first interlevel dielectric (ILD) layer within a trench, after forming the one or more liners, performing a via etch to form a via opening exposing a first conductive line corresponding to a first metallization level, and forming, within the via opening and on the first conductive line, a barrier-less prefilled via including first conductive material.

公开(公告)号：US20210343585A1

公开(公告)日：2021-11-04

申请号：US16861292

申请日：2020-04-29

Applicant: International Business Machines Corporation

Inventor： Brent Anderson ,  Lawrence A. Clevenger ,  Nicholas Anthony Lanzillo ,  Christopher J. Penny ,  Kisik Choi ,  Robert Robison

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522

Abstract: A method of fabricating an integrated circuit includes forming a first trench such that a portion of the first trench is defined by a portion of a first-type of interconnect and depositing a sacrificial spacer liner in the first trench to cover the portion of the first-type of interconnect element. The method further includes forming a dielectric cap on the sacrificial spacer liner and above the first-type of interconnect element, removing the dielectric cap to expose at least a portion of the first-type of interconnect element, and forming a second-type of interconnect element on the exposed first-type of interconnect element.