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公开(公告)号：US11869808B2
公开(公告)日：2024-01-09
申请号：US17481362
申请日：2021-09-22
发明人： Lawrence A. Clevenger , Brent Anderson , Nicholas Anthony Lanzillo , Christopher J. Penny , Kisik Choi , Robert Robison
IPC分类号： H01L21/768 , H01L23/522
CPC分类号： H01L21/76897 , H01L21/7681 , H01L21/76849 , H01L21/76861 , H01L21/76879 , H01L23/5226 , H01L21/76816
摘要： An approach providing a semiconductor wiring structure with a self-aligned top via on a first metal line and under a second metal line. The semiconductor wiring structure includes a plurality of first metal lines in a bottom portion of a first dielectric material. The semiconductor wiring structure includes a top via in a top portion of the first dielectric material, where the top via is over a first metal line of the plurality of first metal lines. The semiconductor wiring structure includes a second dielectric material above each of the plurality of first metal lines except the first metal line of the plurality of first metal lines. Furthermore, the semiconductor wiring structure includes a second metal line above the top via, wherein the second metal line is in a third dielectric material and a hardmask layer that is under the third dielectric material.
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公开(公告)号：US20230210026A1
公开(公告)日：2023-06-29
申请号：US17646210
申请日：2021-12-28
发明人： Timothy Mathew Philip , Kevin W. Brew , Caitlin Camille Stuckey , Rebecca Colby Martin , Robert Robison , Lawrence A. Clevenger
CPC分类号： H01L45/06 , H01L27/24 , H01L45/1286 , H01L45/1608
摘要： A phase change memory (PCM) cell includes a first electrode comprised of a first electrically conductive material, a second electrode comprised of a second electrically conductive material, and a phase change section positioned between the first electrode and the second electrode. The phase change section includes a first phase change material having a first resistance drift coefficient, and a second phase change material having a second resistance drift coefficient that is greater than the first resistance drift coefficient. An axis of the PCM cell extends between the first electrode and the second electrode, and the second phase change material is offset from the first phase change material in a direction that is perpendicular to the axis.
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公开(公告)号：US20230063973A1
公开(公告)日：2023-03-02
申请号：US17446626
申请日：2021-09-01
发明人： Ruilong Xie , Chen Zhang , Brent Anderson , Robert Robison , Ardasheir Rahman , Hemanth Jagannathan
IPC分类号： H01L27/06 , H01L29/78 , H01L21/8234
摘要： An apparatus comprising a plurality of FET columns located on a substrate. A source/drain layer located around the base of the plurality of FET columns. A dielectric layer located around the source/drain layer, wherein a portion of the dielectric layer that is sandwiched between a first portion of the source/drain layer and a second portion of the source/drain layer. A gate layer, wherein the gate layer has a first portion located on top of the source/drain layer, and wherein the gate layer has a second portion located on top of the portion of the dielectric layer that is sandwiched between a first portion of the source/drain layer and a second portion of the source/drain layer.
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公开(公告)号：US20220181255A1
公开(公告)日：2022-06-09
申请号：US17679719
申请日：2022-02-24
发明人： Brent Anderson , Lawrence A. Clevenger , Kisik Choi , Nicholas Anthony Lanzillo , Christopher J. Penny , Robert Robison
IPC分类号： H01L23/522 , H01L21/768 , H01L23/528 , H01L21/311
摘要： Integrated chips include a dielectric layer that includes at least one trench and at least one plug region. A line is formed in the dielectric layer in the at least one trench and terminates at the plug region. A dielectric plug is formed in the plug region.
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5.发明授权公开(公告)号：US11295978B2
公开(公告)日：2022-04-05
申请号：US16861292
申请日：2020-04-29
发明人： Brent Anderson , Lawrence A. Clevenger , Nicholas Anthony Lanzillo , Christopher J. Penny , Kisik Choi , Robert Robison
IPC分类号： H01L21/768 , H01L23/522 , H01L23/528 , H01L45/00 , H01L27/146 , H01L21/02
摘要： A method of fabricating an integrated circuit includes forming a first trench such that a portion of the first trench is defined by a portion of a first-type of interconnect and depositing a sacrificial spacer liner in the first trench to cover the portion of the first-type of interconnect element. The method further includes forming a dielectric cap on the sacrificial spacer liner and above the first-type of interconnect element, removing the dielectric cap to expose at least a portion of the first-type of interconnect element, and forming a second-type of interconnect element on the exposed first-type of interconnect element.
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公开(公告)号：US11276639B2
公开(公告)日：2022-03-15
申请号：US16749476
申请日：2020-01-22
发明人： Brent Anderson , Lawrence A. Clevenger , Kisik Choi , Nicholas Anthony Lanzillo , Christopher J. Penny , Robert Robison
IPC分类号： H01L23/522 , H01L21/768 , H01L21/311 , H01L23/528
摘要： Integrated chips and methods of forming lines in the same include forming a line layer on a substrate. An opening is etched into the line layer that exposes the substrate. A plug is formed in the opening. The line layer is patterned to form a line that terminates at the plug.
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公开(公告)号：US20220028783A1
公开(公告)日：2022-01-27
申请号：US17496252
申请日：2021-10-07
发明人： Brent Alan Anderson , Lawrence A. Clevenger , Christopher J. Penny , Kisik Choi , Nicholas Anthony Lanzillo , Robert Robison
IPC分类号： H01L23/522 , H01L23/528 , H01L23/532
摘要： A semiconductor structure includes a first metallization layer disposed on a first etch stop layer. The first metallization layer includes a first conductive line and a second conductive line, each disposed in a first dielectric layer and extending from the first etch stop layer. The height of the first conductive line is greater than a height of the second conductive line. The semiconductor structure further includes a first via layer comprising a second dielectric layer disposed on a top surface of the first metallization layer and a first via and a second via in the second dielectric layer. The semiconductor structure further includes a first conductive material disposed on a top surface of the first conductive line in the first via. The semiconductor structure further includes a second conductive material disposed on a top surface of the second conductive line in the second via.
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公开(公告)号：US11164777B2
公开(公告)日：2021-11-02
申请号：US16743955
申请日：2020-01-15
发明人： Lawrence A. Clevenger , Brent Anderson , Kisik Choi , Nicholas Anthony Lanzillo , Christopher J. Penny , Robert Robison
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532
摘要： A method of forming a top via is provided. The method includes forming a sacrificial trench layer and conductive trench plug in an interlayer dielectric (ILD) layer on a conductive line. The method further includes forming a cover layer on the ILD layer, sacrificial trench layer, and conductive trench plug, and forming a sacrificial channel layer and a conductive channel plug on the conductive trench plug. The method further includes removing the cover layer and the ILD layer to expose the sacrificial trench layer and the sacrificial channel layer. The method further includes removing the sacrificial trench layer and the sacrificial channel layer, and forming a barrier layer on the conductive channel plug and conductive trench plug.
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公开(公告)号：US11158537B2
公开(公告)日：2021-10-26
申请号：US16750062
申请日：2020-01-23
发明人： Brent Anderson , Lawrence A. Clevenger , Nicholas Anthony Lanzillo , Christopher J. Penny , Kisik Choi , Robert Robison
IPC分类号： H01L21/768 , H01L21/311 , H01L21/02
摘要： Integrated chips and methods of forming the same include forming a conductive layer to a line height. A dielectric layer is formed over the conductive layer to a via height, with at least one opening that exposes a via region of the conductive layer. A conductive via is formed in the opening having the via height. The conductive layer is patterned to form a conductive line having the line height.
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公开(公告)号：US10998193B1
公开(公告)日：2021-05-04
申请号：US16748898
申请日：2020-01-22
发明人： Timothy Mathew Philip , Somnath Ghosh , Daniel James Dechene , Robert Robison , Lawrence A. Clevenger
IPC分类号： H01L21/033 , H01L21/311 , H01L21/02 , H01L21/027 , H01L21/306 , H01L21/3213
摘要： Integrated chips and methods of forming the same include forming a first set of sidewall spacers on a first mandrel at first vertical level. The first mandrel is etched away. A second set of sidewall spacers is formed on a second mandrel at a second vertical level. A portion of the second set of sidewall spacers vertically overlaps with a portion of the first set of sidewall spacers. The second mandrel is etched away. A first hardmask layer is etched, using the vertically overlapping first set of sidewall spacers and second set of sidewall spacers as a mask.
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