公开(公告)号：US5872948A

公开(公告)日：1999-02-16

申请号：US616613

申请日：1996-03-15

申请人： Soummya Mallick ,  Rajesh Bikhubhai Patel ,  Romesh Mangho Jessani ,  Michael Putrino

发明人： Soummya Mallick ,  Rajesh Bikhubhai Patel ,  Romesh Mangho Jessani ,  Michael Putrino

IPC分类号： G06F9/38 ,  G06F9/28

CPC分类号： G06F9/3836 ,  G06F9/384 ,  G06F9/3857

摘要： A processor and method for out-of-order execution of instructions are disclosed which fetch a first and a second instruction, wherein the first instruction precedes the second instruction in a program order. A determination is made whether execution of the second instruction is subject to execution of the first instruction. In response to a determination that execution of the second instruction is subject to execution of the first instruction, the second instruction is selectively executed prior to the first instruction in response to a parameter of at least one of the first and second instructions. In one embodiment, the parameter is an execution latency parameter of the first and second instructions.

摘要翻译： 公开了用于执行指令的处理器和方法，其提取第一和第二指令，其中第一指令以程序顺序在第二指令之前。 确定第二指令的执行是否受到第一指令的执行。 响应于第二指令的执行被执行第一指令的确定，响应于第一和第二指令中的至少一个指令的参数在第一指令之前选择性地执行第二指令。 在一个实施例中，该参数是第一和第二指令的执行等待时间参数。

公开(公告)号：US5805907A

公开(公告)日：1998-09-08

申请号：US726370

申请日：1996-10-04

申请人： Albert John Loper ,  Soummya Mallick

发明人： Albert John Loper ,  Soummya Mallick

IPC分类号： G06F1/04 ,  G06F1/32 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F9/48 ,  G06F12/08

CPC分类号： G06F9/30087 ,  G06F1/32 ,  G06F12/0864 ,  G06F9/30047 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3869 ,  G06F9/3885 ,  G06F2212/1028 ,  Y02B60/1225

摘要： While dispatch circuitry operates in a first power mode, per cycle of the dispatch circuitry, up to N number of instructions are dispatched to execution circuitry for execution, where N is an integer number and N>1. While the dispatch circuitry operates in a second power mode, per cycle of the dispatch circuitry, up to M number of instructions are dispatched to the execution circuitry for execution, where M is an integer number and 0

摘要翻译： 当调度电路以第一功率模式工作时，在调度电路的每个周期中，最多N个指令被调度到执行电路以进行执行，其中N是整数并且N> 1。 当调度电路在第二功率模式下工作时，在调度电路的每个周期，多达M个指令被分派到执行电路执行，其中M是整数，0

公开(公告)号：US5802572A

公开(公告)日：1998-09-01

申请号：US616612

申请日：1996-03-15

申请人： Rajesh Bhikhubhai Patel ,  Soummya Mallick

发明人： Rajesh Bhikhubhai Patel ,  Soummya Mallick

IPC分类号： G06F12/08 ,  G06F13/00 ,  G06F12/00

CPC分类号： G06F12/0815 ,  G06F12/0804

摘要： A write-back cache memory and method for maintaining coherency within a write-back cache memory are disclosed. The write-back cache memory includes a number of cache lines for storing data associated with addresses within an associated memory. Each of the cache lines comprises multiple byte sets. The write-back cache memory also includes coherency indicia for identifying each byte set among the multiple byte sets within a cache line which contains data that differs from data stored in corresponding addresses within the associated memory. The write-back cache memory further includes cache control logic, which, upon replacement of a particular cache line within the write-back cache memory, writes only identified byte sets to the associated memory, such that memory accesses and bus utilization are minimized.

摘要翻译： 公开了一种用于在回写高速缓冲存储器内保持一致性的回写高速缓冲存储器和方法。 回写高速缓冲存储器包括用于存储与相关存储器内的地址相关联的数据的多条高速缓存行。 每个高速缓存行包括多个字节集。 回写高速缓冲存储器还包括用于识别高速缓存行内的多个字节集合中的每个字节集合的一致性标记，其包含与存储在相关联的存储器内的相应地址中的数据不同的数据。 回写高速缓冲存储器还包括高速缓存控制逻辑，其在替换回写高速缓冲存储器中的特定高速缓存行之后，仅将识别的字节集写入相关联的存储器，使得存储器访问和总线利用被最小化。

公开(公告)号：US5802340A

公开(公告)日：1998-09-01

申请号：US518000

申请日：1995-08-22

申请人： Soummya Mallick ,  Rajesh B. Patel

发明人： Soummya Mallick ,  Rajesh B. Patel

IPC分类号： G06F9/38

CPC分类号： G06F9/3865 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3857

摘要： A method for speculatively performing store instructions in a parallel processing computer system, the computer system including a completion buffer unit, includes comparing statuses between a first store instruction and at least one second instruction in the completion buffer unit, the at least one second instruction scheduled for completion before the first store instruction, and speculatively completing the first store instruction before the at least one second instruction when the statuses of the first store instruction do not conflict with the at least one second instruction. In another method aspect, speculatively performing store instructions includes forming a general purpose register (GPR) allocation deallocation table, the table including status fields for a plurality of instructions in a completion buffer unit, comparing the status fields of each of the plurality of instructions to a store instruction of the plurality of instructions, and speculatively completing the store instruction when the status fields for the store instruction do not conflict with the status fields for the plurality of instructions.

摘要翻译： 一种用于在并行处理计算机系统中推测性地执行存储指令的方法，所述计算机系统包括完成缓冲器单元，包括比较第一存储指令与完成缓冲器单元中的至少一个第二指令之间的状态，所述至少一个第二指令被调度 在第一存储指令之前完成，并且当第一存储指令的状态不与至少一个第二指令冲突时，在至少一个第二指令之前推测地完成第一存储指令。 在另一方法方面，推测性地执行的存储指令包括形成通用寄存器（GPR）分配解除分配表，该表包括完成缓冲器单元中的多个指令的状态字段，将多个指令中的每一个的状态字段与 多个指令的存储指令，并且当存储指令的状态字段不与多个指令的状态字段冲突时，推测地完成存储指令。

公开(公告)号：US5765215A

公开(公告)日：1998-06-09

申请号：US519556

申请日：1995-08-25

申请人： Muhammad Afsar ,  Soummya Mallick ,  Rajesh B. Patel

发明人： Muhammad Afsar ,  Soummya Mallick ,  Rajesh B. Patel

IPC分类号： G06F9/312 ,  G06F9/38 ,  G06F9/26 ,  G06F12/02

CPC分类号： G06F9/30043 ,  G06F9/3836 ,  G06F9/384

摘要： A method and system are disclosed for managing the deallocation of a rename buffer allocated to an update instruction within a processor. The processor has a number of rename buffers for temporarily storing information associated with instructions executed by the processor, a number of registers, and a memory. According to the present invention, an update instruction is dispatched to the processor for execution. A particular rename buffer is then allocated to the update instruction. An effective address is generated for the update instruction, wherein the effective address specifies an address within the memory to be accessed by the update instruction. Next, the effective address is stored within the particular rename buffer. Prior to completion of the access to the effective address within memory, the effective address is transferred from the particular rename buffer to a particular one of the number of registers. Thereafter, the particular rename buffer is deallocated, wherein processor performance is enhanced by improved rename buffer availability.

摘要翻译： 公开了一种用于管理分配给处理器内的更新指令的重命名缓冲器的分配的方法和系统。 处理器具有多个重命名缓冲器，用于临时存储与由处理器执行的指令相关联的信息，多个寄存器和存储器。 根据本发明，更新指令被发送到处理器执行。 然后将特定的重命名缓冲区分配给更新指令。 生成更新指令的有效地址，其中，有效地址指定要由更新指令访问的存储器内的地址。 接下来，有效地址存储在特定的重命名缓冲区内。 在访问存储器内的有效地址之前，将有效地址从特定重命名缓冲区传送到寄存器数目中的特定一个。 此后，取消分配特定重命名缓冲区，其中通过改进的重命名缓冲器可用性来增强处理器性能。

公开(公告)号：US5765191A

公开(公告)日：1998-06-09

申请号：US641060

申请日：1996-04-29

申请人： Albert John Loper ,  Soummya Mallick ,  Rajesh Bhikhubhai Patel ,  Michael Putrino

发明人： Albert John Loper ,  Soummya Mallick ,  Rajesh Bhikhubhai Patel ,  Michael Putrino

IPC分类号： G06F12/08 ,  G06F12/12

CPC分类号： G06F12/123

摘要： A method for implementing a four-way least recently used cache line replacement scheme in a four-way cache memory is disclosed. The cache memory includes multiple cache lines, and each cache line includes four congruence sets. In accordance with the present disclosure, a 5-bit Least Recently Used (LRU) field is associated with each of the cache lines within the cache memory. For a particular cache line, a set number of a least recently used set among the four congruence sets is stored in any two bits of the LRU field associated with that cache line. Next, a set number of the second least recently used set among the four congruence sets is stored in another two bits of the same LRU field associated with the same cache line. Finally, a last bit of the 5-bit LRU field is set to a specific state in response to a determination of which one of the remaining two sets is the second most recently used set.

摘要翻译： 公开了一种用于在四路高速缓冲存储器中实现四路最少使用的高速缓存行替换方案的方法。 高速缓冲存储器包括多个高速缓存行，并且每个高速缓存行包括四个一致集合。 根据本公开，5位最近使用（LRU）字段与高速缓冲存储器内的每个高速缓存行相关联。 对于特定的高速缓存行，四个同余集中的最近最少使用的集合的集合数存储在与该高速缓存行相关联的LRU字段的任何两个位中。 接下来，将四个同余集合中的第二最近使用的集合的集合数存储在与相同高速缓存行相关联的相同LRU字段的另外两个比特中。 最后，响应于确定剩余两组中的哪一组是最近使用的第二组，将5位LRU字段的最后一位设置为特定状态。

公开(公告)号：US5758117A

公开(公告)日：1998-05-26

申请号：US572458

申请日：1995-12-14

申请人： Rajesh Bhikhubhai Patel ,  Soummya Mallick

发明人： Rajesh Bhikhubhai Patel ,  Soummya Mallick

IPC分类号： G06F9/38

CPC分类号： G06F9/384 ,  G06F9/3836 ,  G06F9/3857

摘要： A method for reducing dispatch stalls includes tracking allocation and deallocation of real rename buffers for instructions dispatched by a dispatch unit, and providing at least one virtual rename buffer for allocation of an instruction when the real rename buffers have been allocated. The method further includes tagging the instruction allocated to the at least one virtual rename buffer with a rename buffer busy signal, wherein the rename buffer busy signal indicates to an execution unit that the instruction cannot be completed. An efficient system for utilization of rename buffers in a superscalar processor includes a plurality of rename buffers, a dispatch unit coupled to the plurality of rename buffers, and an allocation/deallocation table coupled to the dispatch unit and the plurality of rename buffers. Further, the table includes a plurality of real rename buffer slots and at least one virtual rename buffer slot. Additionally, a rename busy signal is provided for an instruction allocated to the at least one virtual rename buffer slot.

摘要翻译： 一种用于减少调度停顿的方法包括对由调度单元调度的指令的真实重命名缓冲器的跟踪分配和释放，以及当已经分配了实际重命名缓冲器时提供用于分配指令的至少一个虚拟重命名缓冲器。 该方法还包括使用重命名缓冲区忙信号标记分配给至少一个虚拟重命名缓冲器的指令，其中重命名缓冲器忙信号向执行单元指示该指令不能完成。 用于在超标量处理器中使用重命名缓冲器的有效系统包括多个重命名缓冲器，耦合到多个重命名缓冲器的调度单元以及耦合到调度单元和多个重命名缓冲器的分配/取消分配表。 此外，该表包括多个真实重命名缓冲器时隙和至少一个虚拟重命名缓冲器时隙。 此外，为分配给至少一个虚拟重命名缓冲器时隙的指令提供重命名忙信号。

公开(公告)号：US5664120A

公开(公告)日：1997-09-02

申请号：US519557

申请日：1995-08-25

申请人： Muhammad Afsar ,  Soummya Mallick

发明人： Muhammad Afsar ,  Soummya Mallick

IPC分类号： G06F9/38

CPC分类号： G06F9/3836 ,  G06F9/384

摘要： A method and apparatus for executing instructions within a processor which completes instructions according to a program order are disclosed. The processor has multiple rename buffers for temporarily storing results of instructions, a number of registers, and an execution unit. The execution unit has a reservation data structure comprising a plurality of entries for storing instructions to be executed by the execution unit and a single operand buffer for storing one or more operands of a single instruction. According to the present invention, an instruction is received at the execution unit. The instruction is then stored within the reservation data structure within the execution unit in association with information specifying a source of an operand of the instruction. Sources of operands of instructions include the rename buffers and the registers. A determination is then made if the instruction is a next instruction to be executed by the execution unit. In response to a determination that the instruction is the next instruction to be executed by the execution unit, the operand of the instruction is loaded from the specified source into the single operand entry. The instruction is then executed within the execution unit utilizing the operand within the single operand entry. By utilizing only a single operand buffer, processor chip area allocated to operand storage within the execution unit is reduced.

摘要翻译： 公开了一种在处理器内执行根据程序顺序完成指令的指令的方法和装置。 处理器具有用于临时存储指令结果，多个寄存器和执行单元的多个重命名缓冲器。 执行单元具有包括用于存储由执行单元执行的指令的多个条目的预约数据结构和用于存储单个指令的一个或多个操作数的单个操作数缓冲器。 根据本发明，在执行单元处接收指令。 该指令与指定该指令的操作数的源的信息相关联地存储在执行单元内的预约数据结构内。 指令操作数的来源包括重命名缓冲区和寄存器。 然后，如果指令是由执行单元执行的下一个指令，则进行确定。 响应于指令是由执行单元执行的下一条指令，指令的操作数从指定的源加载到单个操作数条目中。 然后使用单个操作数条目内的操作数，在执行单元内执行该指令。 通过仅使用一个操作数缓冲器，减少了分配给执行单元内操作数存储的处理器芯片面积。