公开(公告)号：US20160148134A1

公开(公告)日：2016-05-26

申请号：US14948832

申请日：2015-11-23

申请人： James Fields

发明人： James Fields

IPC分类号： G06Q10/06

CPC分类号： G06Q10/06311

摘要： A method of providing an electronic bail posting service is used to create a network of bail-posting agents and companies. The method also allows companies to hire bounty hunters to retrieve clients. A server is used manage a plurality of company accounts, agent accounts, and bounty hunter accounts. Each of these accounts is used by companies, posting agents, and bounty hunters to network with each other. An employer computing device displays a plurality of feature options to be selected. The desired feature that is selected corresponds with a job request that is to be sent to a plurality of desired recipients which are designated by the server. A job request is sent to the desired recipients and a job acceptance confirmation is generated when a work-willing recipient accepts the job request. A job completion receipt is sent to the employer computing device once the job request has been fulfilled.

摘要翻译： 使用提供电子保释服务的方法来创建一个保释代理和公司网络。 该方法还允许公司雇用赏金猎人检索客户端。 使用服务器管理多个公司帐户，代理帐户和赏金猎人帐户。 这些帐户中的每一个都由公司，过帐代理和赏金猎人用来互相联网。 雇主计算设备显示要选择的多个特征选项。 所选择的特征对应于要发送到由服务器指定的多个期望的接收者的作业请求。 作业请求被发送到所需的收件人，并且当工作愿意的接收者接受作业请求时，生成作业接受确认。 一旦完成了工作请求，就将工作完成收据发送给雇主计算设备。

公开(公告)号：US20060190685A1

公开(公告)日：2006-08-24

申请号：US11054182

申请日：2005-02-09

申请人： Richard Arndt ,  George Daly ,  James Fields ,  Warren Maule

发明人： Richard Arndt ,  George Daly ,  James Fields ,  Warren Maule

IPC分类号： G06F13/28 ,  G06F13/36

CPC分类号： G06F12/0837 ,  G06F12/084 ,  G06F12/1081 ,  G06F2212/1041 ,  G06F2212/683

摘要： A method and apparatus for invalidating entries within a translation control entry (TCE) cache are disclosed. A host bridge is coupled between a group of processors and a group of adaptors. The host bridge includes a TCE cache. The TCE cache contains the most-recently use copies of TCEs in a TCE table located in a system memory. In response to a modification to a TCE in the TCE table by one of the processors, a memory mapped input/output (MMIO) Store is sent to a TCE invalidate register to specify an address of the modified TCE. The data within the TCE invalidate register is then utilized to generate a command for invalidating an entry in the TCE cache containing an unmodified copy of the modified TCE in the TCE table. The command is subsequently sent to the host bridge to invalidate the entry in the TCE cache.

摘要翻译： 公开了一种使翻译控制条目（TCE）高速缓存内的条目无效的方法和装置。 主机桥耦合在一组处理器和一组适配器之间。 主机桥包括TCE缓存。 TCE缓存包含位于系统内存中的TCE表中最近使用的TCE的副本。 响应于一个处理器对TCE表中的TCE进行修改，将存储器映射的输入/输出（MMIO）存储发送到TCE无效寄存器，以指定修改的TCE的地址。 然后使用TCE无效寄存器内的数据来产生用于使包含TCE表中修改的TCE的未修改副本的TCE缓存中的条目无效的命令。 该命令随后发送到主机桥，使TCE缓存中的条目无效。

公开(公告)号：US20060179248A1

公开(公告)日：2006-08-10

申请号：US11055640

申请日：2005-02-10

申请人： James Fields ,  Sanjeev Ghai ,  Warren Maule ,  Jeffrey Stuecheli

发明人： James Fields ,  Sanjeev Ghai ,  Warren Maule ,  Jeffrey Stuecheli

IPC分类号： G06F13/28

CPC分类号： G06F11/1064 ,  G06F12/0831

摘要： A cache coherent data processing system includes a plurality of processing units each having at least an associated cache, a system memory, and a memory controller that is coupled to and controls access to the system memory. The system memory includes a plurality of storage locations for storing a memory block of data, where each of the plurality of storage locations is sized to store a sub-block of data. The system memory further includes metadata storage for storing metadata, such as a domain indicator, describing the memory block. In response to a failure of a storage location for a particular sub-block among the plurality of sub-blocks, the memory controller overwrites at least a portion of the metadata in the metadata storage with the particular sub-block of data.

摘要翻译： 高速缓存一致性数据处理系统包括多个处理单元，每个处理单元至少具有相关联的高速缓存，系统存储器和存储器控制器，其耦合到并控制对系统存储器的访问。 系统存储器包括用于存储数据的存储块的多个存储位置，其中多个存储位置中的每一个被设置为存储数据的子块。 系统存储器还包括用于存储描述存储器块的诸如域指示符的元数据的元数据存储。 响应于多个子块中的特定子块的存储位置的故障，存储器控制器使用特定的数据子块来覆盖元数据存储器中的元数据的至少一部分。

公开(公告)号：US20060179184A1

公开(公告)日：2006-08-10

申请号：US11055675

申请日：2005-02-10

申请人： James Fields ,  Paul Lecocq ,  Brian Monwai ,  Thomas Pflueger ,  Kevin Reick ,  Timothy Skergan ,  Scott Swaney

发明人： James Fields ,  Paul Lecocq ,  Brian Monwai ,  Thomas Pflueger ,  Kevin Reick ,  Timothy Skergan ,  Scott Swaney

IPC分类号： G06F3/06 ,  G06F3/02 ,  G06F3/00

CPC分类号： G06F15/161

摘要： In-band firmware executes instructions which cause commands to be sent on a coherency fabric. Fabric snoop logic monitors the coherency fabric for command packets that target a resource in one of the support chips attached via an FSI link. Conversion logic converts the information from the fabric packet into an FSI protocol. An FSI command is transmitted via the FSI transmit link to an FSI slave of the intended support chip. An FSI receive link receives response data from the FSI slave of the intended support chip. Conversion logic converts the information from the support chip received via the FSI receive link into the fabric protocol. Response packet generation logic generates the fabric response packet and returns it on the coherency fabric. An identical FSI link between a support processor and support chips allows direct access to the same resources on the support chips by out-of-band firmware.

摘要翻译： 带内固件执行指令，使指令在一致性结构上发送。 Fabric Snoop逻辑监视针对通过FSI链接附加的支持芯片之一的资源的命令包的一致性结构。 转换逻辑将信息从Fabric数据包转换为FSI协议。 FSI命令通过FSI传输链路发送到预期支持芯片的FSI从站。 FSI接收链路从预期的支持芯片的FSI从站接收响应数据。 转换逻辑将从通过FSI接收链路接收的支持芯片的信息转换为结构协议。 响应分组生成逻辑生成结构响应分组并将其返回到一致性结构上。 支持处理器和支持芯片之间的相同FSI链路允许通过带外固件直接访问支持芯片上的相同资源。

公开(公告)号：US20060176897A1

公开(公告)日：2006-08-10

申请号：US11055404

申请日：2005-02-10

申请人： James Fields ,  Paul Lecocq ,  Brian Monwai ,  Thomas Pflueger ,  Kevin Reick ,  Timothy Skergan ,  Scott Swaney

发明人： James Fields ,  Paul Lecocq ,  Brian Monwai ,  Thomas Pflueger ,  Kevin Reick ,  Timothy Skergan ,  Scott Swaney

IPC分类号： H04L12/66

CPC分类号： G06F15/7842

摘要： A method and apparatus are provided for a support interface for memory-mapped resources. A support processor sends a sequence of commands over and FSI interface to a memory-mapped support interface on a processor chip. The memory-mapped support interface updates memory, memory-mapped registers or memory-mapped resources. The interface uses fabric packet generation logic to generate a single command packet in a protocol for the coherency fabric which consists of an address, command and/or data. Fabric commands are converted to FSI protocol and forwarded to attached support chips to access the memory-mapped resource, and responses from the support chips are converted back to fabric response packets. Fabric snoop logic monitors the coherency fabric and decodes responses for packets previously sent by fabric packet generation logic. The fabric snoop logic updates status register and/or writes response data to a read data register. The system also reports any errors that are encountered.

摘要翻译： 提供了一种用于存储器映射资源的支持接口的方法和装置。 支持处理器将一系列命令和FSI接口发送到处理器芯片上的存储器映射支持接口。 内存映射支持接口更新内存，内存映射寄存器或内存映射资源。 该接口使用结构数据包生成逻辑在由地址，命令和/或数据组成的一致性结构的协议中生成单个命令分组。 Fabric命令转换为FSI协议，并转发到附加的支持芯片以访问内存映射资源，并将来自支持芯片的响应转换回Fabric响应数据包。 Fabric监听逻辑监视一致性结构，并解码先前由Fabric数据包生成逻辑发送的数据包的响应。 织物窥探逻辑更新状态寄存器和/或将响应数据写入读取数据寄存器。 系统还报告遇到的任何错误。

公开(公告)号：US20070061630A1

公开(公告)日：2007-03-15

申请号：US11225639

申请日：2005-09-13

申请人： James Fields ,  Benjiman Goodman ,  Praveen Reddy

发明人： James Fields ,  Benjiman Goodman ,  Praveen Reddy

IPC分类号： G06F11/00

CPC分类号： G06F11/0751 ,  G06F11/076 ,  G06F11/0793

摘要： A data processing system, method, and computer-usable medium for recovering from a hang condition in a data processing system. The data processing system includes a collection of coupled processing units. The processing units include a collection of processing unit components such as, two or more processing cores, and a cache array, a processor core master, a cache snooper, and a local hang manager. The local hang manager determines whether at least one component out of the collection of processing unit components has entered into a hang condition. If the local hang manager determines at least one component has entered into a hang condition, a throttling manager throttles the performance of the processing unit in an attempt to break the at least one component out of the hang condition.

摘要翻译： 一种用于从数据处理系统中的挂起状态恢复的数据处理系统，方法和计算机可用介质。 数据处理系统包括耦合处理单元的集合。 处理单元包括诸如两个或更多个处理核心的处理单元组件的集合，以及高速缓存阵列，处理器核心主控器，高速缓存侦听器和本地挂起管理器。 本地挂起管理器确定处理单元组件的集合中的至少一个组件是否已进入挂起状态。 如果本地挂起管理器确定至少有一个组件已进入挂起状态，则节流管理器会阻止处理单元的性能，以试图将至少一个组件从挂起状态中断。

公开(公告)号：US20060187818A1

公开(公告)日：2006-08-24

申请号：US11054288

申请日：2005-02-09

申请人： James Fields ,  Michael Floyd ,  Benjiman Goodman ,  Paul Lecocq ,  Praveen Reddy

发明人： James Fields ,  Michael Floyd ,  Benjiman Goodman ,  Paul Lecocq ,  Praveen Reddy

IPC分类号： H04J1/16

CPC分类号： G06F11/0793 ,  G06F11/0724

摘要： A method, apparatus, and computer instructions are provided by the present invention to automatically recover from a failed node concurrent maintenance operation. A control logic is provided to send a first test command to processors of a new node. If the first test command is successful, a second test command is sent to all processors or to the remaining nodes if nodes are removed. If the second command is successful, system operation is resumed with the newly configured topology with either nodes added or removed. If the response is incorrect or a timeout has occurred, the control logic restores values to the current mode register and sends a third test command to check for an error. A fatal system attention is sent to a service processor or system software if an error is encountered. If no error, system operation is resumed with previously configured topology.

摘要翻译： 本发明提供了一种方法，装置和计算机指令，以便从故障节点并发维护操作中自动恢复。 提供控制逻辑以将第一测试命令发送到新节点的处理器。 如果第一个测试命令成功，则将第二个测试命令发送到所有处理器或其他节点，如果节点被删除。 如果第二个命令成功，则使用添加或删除节点的新配置的拓扑恢复系统操作。 如果响应不正确或发生超时，控制逻辑将恢复到当前模式寄存器的值，并发送第三个测试命令来检查错误。 如果遇到错误，致命的系统注意事项将发送到服务处理器或系统软件。 如果没有错误，则使用先前配置的拓扑恢复系统操作。

公开(公告)号：US20060184706A1

公开(公告)日：2006-08-17

申请号：US11055847

申请日：2005-02-11

申请人： James Fields ,  Michael Floyd ,  Paul Lecocq

发明人： James Fields ,  Michael Floyd ,  Paul Lecocq

IPC分类号： G06F13/14

CPC分类号： G06F13/1652 ,  Y10S370/916

摘要： The present invention, a multiprocessor chip pervasive command interface, collects different types of pervasive commands into individual queues for each command type. As permitted by various grouping rules, valid commands are grouped together into one single command and placed on a functional interchip communications bus. This grouping of commands maximizes pervasive command bandwidth while the use of the functional bus minimizes the number of interchip connections.

公开(公告)号：US20060101226A1

公开(公告)日：2006-05-11

申请号：US10982354

申请日：2004-11-05

申请人： Michael Benhase ,  Robert Cargnoni ,  James Fields ,  Michael Mayfield ,  Bruce Mealey

发明人： Michael Benhase ,  Robert Cargnoni ,  James Fields ,  Michael Mayfield ,  Bruce Mealey

IPC分类号： G06F12/10

CPC分类号： G06F12/1081 ,  G06F2212/206

摘要： Provided are a method, system, and program for transferring data directed to virtual memory addresses to a device memory. Indicator bits are set for ranges of device memory addresses in a device accessible over an Input/Output (I/O) bus indicating whether gathering is enabled for the device memory address ranges. Transfer operations are processed to transfer data to contiguous device memory addresses in the device. A determination is made as to whether the indicator bits for the contiguous device memory addresses indicate that gathering is enabled. A single bus I/O transaction is generated to transfer data for the contiguous device memory addresses over the I/O bus in response to determining that the indicator bits for the contiguous device memory addresses indicate that gathering is enabled.

摘要翻译： 提供了用于将指向虚拟存储器地址的数据传送到设备存储器的方法，系统和程序。 指示位设置在可通过输入/输出（I / O）总线访问的设备中的设备存储器地址的范围，指示是否对设备存储器地址范围进行采集。 处理传输操作将数据传输到设备中的连续设备存储器地址。 确定连续设备存储器地址的指示符位是否指示该采集被启用。 响应于确定连续设备存储器地址的指示符位表示启用了集合，生成单总线I / O事务以通过I / O总线传送连续设备存储器地址的数据。